Avalanche photodiodes, which operate above the breakdown voltage in Geiger mode connected with avalanche-quenching circuits, can be used to detect single photons and are therefore called singlephoton avalanche diodes SPAD's. Circuit configurations suitable for this operation mode are critically analyzed and their relative merits in photon counting and timing applications are assessed. Simple passive-quenching circuits (PQC's), which are useful for SPAD device testing and selection, have fairly limited application. Suitably designed active-quenching circuits (AQC's) make it possible to exploit the best performance of SPAD's. Thick silicon SPAD's that operate at high voltages (250-450 V) have photon detection efficiency higher than 50% from 540- to 850-nm wavelength and still ~3% at 1064 nm. Thin silicon SPAD's that operate at low voltages (10-50 V) have 45% efficiency at 500 nm, declining to 10% at 830 nm and to as little as 0.1% at 1064 nm. The time resolution achieved in photon timing is 20 ps FWHM with thin SPAD's; it ranges from 350 to 150 ps FWHM with thick SPAD's. The achieved minimum counting dead time and maximum counting rate are 40 ns and 10 Mcps with thick silicon SPAD's, 10 ns and 40 Mcps with thin SPAD's. Germanium and III-V compound semiconductor SPAD's extend the range of photon-counting techniques in the near-infrared region to at least 1600-nm wavelength.

GHz. Figure 6(b) shows the measured phase noise of the injection signal and locked output signal for the divide-by-2 ILFD. At 100 KHz offset frequency, the phase noise of the injection signal is Ϫ100.6 dBc/Hz, and the phase noise of the locked signal is Ϫ106.8 dBc/Hz. At low offset frequency, the phase noise of the locked output spectrum is lower than that of injection reference by 6.2 dBc/Hz. Figure 7 shows the measured time-domain output waveforms from two QILFD output buffers by using the Agilent 54855A Infiniium oscilloscope. The average output phase error is about 0.28°introduced partly by cables and connectors. Table 2 is the performance comparison of the existing QILFDs. Figure 8 shows the measured relationship between input sensitivity and operating frequency of the divide-by-2 QILFD at V dd ϭ 0.7 V. The locking range is from 9.9 to 11.1 GHz at the input power of 0 dBm and V bias ϭ 0.6 V and the power is 3.37 mW. CONCLUSIONIn this paper, a new LC-tank divide-by-2 QILFD has been proposed. The QILFD consists of a back-gate coupling quadrature VCO and a pair of injection transistors for coupling injection signal to the resonators. The new quadrature VCO uses two differential VCOs with different gate and drain dc biases and a back-coupling mechanism so that the power can be lowered, and the trade-off of power and locking range can be optimized by tuning the gate bias for RF application. The quadrature ILFD has been successfully implemented in the TSMC 0.18 m CMOS process. At the supply voltage of 0.8 V and gate bias ϭ 0.7 V of switching MOSFETs, the core power consumption of the proposed circuit is about 5.72 mW. At the input power of 0 dBm, the total operation locking range is 5.1 GHz, from 8.2 to 13.3 GHz, in the divide-by-2 mode. The phase deviation between in-phase and quadrature-phase outputs is about 1.28°. CENTER-FED CIRCULAR EPSILON-NEGATIVE ZEROTH-ORDER

A new concept for quadrature coupling of LC oscillators is introduced and demonstrated on a 5-GHz CMOS voltage-controlled oscillator (VCO). It uses the second harmonic of the outputs to couple the oscillators. The technique provides quadrature over a wide tuning range without introducing any increase in phase noise or power consumption. The VCO is tunable between 4.57 and 5.21 GHz and has a phase noise lower than -124 dBc/Hz at 1-MHz offset over the entire tuning range. The worst-case measured image rejection is 33 dB. The circuit draws 8.75 mA from a 2.5-V supply

The tuning curve of an LC-tuned voltage-controlled oscillator (VCO) substantially deviates from the ideal curve 1/√(LC(V)) when a varactor with an abrupt C(V) characteristic is adopted and the full oscillator swing is applied directly across the varactor. The tuning curve becomes strongly dependent on the oscillator bias current. As a result, the practical tuning range is reduced and the upconverted flicker noise of the bias current dominates the 1/f3 close-in phase noise, even if the waveform symmetry has been assured. A first-order estimation of the tuning curve for MOS-varactor-tuned VCOs is provided. Based on this result, a simplified phase-noise model for double cross-coupled VCOs is derived. This model can be easily adapted to cover other LC-tuned oscillator topologies. The theoretical analyses are experimentally validated with a 0.25 μm CMOS fully integrated VCO for 5 GHz wireless LAN receivers. By eliminating the bias current generator in a second oscillator, the close-in phase noise improves by 10 dB and features -70 dBc/Hz at 10 kHz offset. The 1/f2 noise is -132 dBc/Hz at 3 MHz offset. The tuning range spans from 4.6 to 5.7 GHz (21%) and the current consumption is 2.9 mA

No abstract

We present a theory of the noise transfer in LC tuned oscillators accounting for the nonlinear operation of the transconductor. We show that the transconductor switching causes a folding of the wide-band noise such as the thermal noise of the spreading resistance of the bipolar transistors and the noise of the tail current generator. The effect is similar to what happens in sampled systems, however, for a careful evaluation of the oscillator phase noise, the correlations between the folded terms is of chief importance. We show how to account for the effect, we assess the impact on the oscillator noise performance and we give the guidelines for the circuit optimization.

No abstract

This paper presents a physical derivation of phase noise in source-coupled-logic frequency dividers. This analysis takes into account both white and flicker noise sources and is verified on two 32/33 dual-modulus prescalers integrated in a 0.35-μm CMOS process. Design techniques for high-speed and low-noise operation are provided. The two integrated prescalers are identical apart from a synchronizing flip-flop at the output of one of them. The measured phase spectra are in good agreement with the estimates and demonstrate that the final synchronization allows a better trade-off between noise and power consumption. The maximum operating frequency is 3 GHz, the power consumption is 27 mW and the phase noise floor is -163 dBc/Hz referred to the 78-MHz output