Phase noise in digital frequency dividers

Levantino, Salvatore; Romanò, L.; Pellerano, Stefano; Samori, Carlo; Lacaita, A.L.

doi:10.1109/jssc.2004.826338

Cited by 102 publications

(71 citation statements)

References 15 publications

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“…The same happens to the transistors M5 and M6. Neglecting the transistor's on resistance, the schematic of the latch can be simplified as shown in Fig.3(b) [8], with R L and C L the effective load resistance and capacitance. Fig.3(b) is exactly the same as the schematic of the CML delay unit as shown in Fig.1(b).…”

Section: B Comparing the Vcdl And Dff Chain Jittermentioning

confidence: 99%

See 2 more Smart Citations

Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers

Gao

Klumperink

Nauta

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when both are realized with current mode logic (CML) circuits and white noise is assumed. This is due to the factor that the shift register MPCG has no jitter accumulation from one clock phase to the other as in the DLL based MPCG. For N-phase clock generation, the shift register MPCG needs a reference clock with N times higher frequency and thus requires a VCO with higher frequency than the DLL counterpart. However, we can show that this does not lead to additional power consumption.

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Section: B Comparing the Vcdl And Dff Chain Jittermentioning

confidence: 99%

“…The jitter variance of the circuit shown in Fig.3(b) can be predicted using the analysis presented in [8] as:…”

Section: B Comparing the Vcdl And Dff Chain Jittermentioning

confidence: 99%

See 1 more Smart Citation

Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers

Gao

Klumperink

Nauta

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…This stringent settling time requirement is far shorter than that of a conventional SSCG. Figure 3 shows a block diagram of a conventional SSCG based on a fractional PLL [3,4,6,[10][11][12][13][14][15][16][17][18][19][20]. It consists of a phase frequency detector (PFD), a charge pump (CP), a 3rd order loop filter (LF), a voltage controlled oscillator (VCO), a multimodulus divider (MMD), a programmable counter (PGC), a ΣΔ modulator (ΣΔ), and a wave generator (WG).…”

Section: Introductionmentioning

confidence: 99%

A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications

Kimura

Suzuki

Noto

2015

Journal of Electrical and Computer Engineering

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A low-jitter fractional spread-spectrum clock generator (SSCG) utilizing a fast-settling dual-charge-pump (CP) technique is developed for serial-advanced technology attachment (SATA) applications. The dual-CP architecture reduces a design area to 60% by shrinking an effective capacitance of a loop filter. Moreover, the settling-time is reduced by 4 s to charge a current to the capacitor by only main-CP in initial period in settling-time. The SSCG is fabricated in a 0.13 m CMOS and achieves settling time of 3.91 s faster than 8.11 s of a conventional SSCG. The random jitter and total jitter at 250 cycles at 1.5 GHz are less than 3.2 and 10.7 psrms, respectively. The triangular modulation signal frequency is 31.5 kHz and the modulation deviation is from −5000 ppm to 0 ppm at 1.5 GHz. The EMI reduction is 10.0 dB. The design area and power consumption are 300 × 700 m and 18 mW, respectively.

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“…Therefore, stages can be analyzed only one at a time. The first analytical model was proposed in [7]. This model was an application of a VCO jitter model described in [1] to a current-mode logic (CML) frequency divider, and it models generation of jitter as a linear time-invariant (LTI) process.…”

Section: Introductionmentioning

confidence: 99%

A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers

Aleksic

Nedovic

Current

et al. 2005

Lecture Notes in Computer Science

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Abstract.A new method for predicting timing jitter caused by device noise in current-mode logic (CML) frequency dividers is presented. Device noise transformation into jitter is modeled as a linear time-varying (LTV) process, as opposed to a previously published method, which models jitter generation as a linear time-invariant (LTI) process. Predictions obtained using the LTV method match jitter values obtained through exhaustive simulation with an error of up to 7.7 %, whereas errors of the jitter predicted by the LTI method exceed 57 %.

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Phase noise in digital frequency dividers

Cited by 102 publications

References 15 publications

Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers

Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers

A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications

A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers

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