Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers

Abstract

Abstract-This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when both are realized with current mode logic (CML) circuits and white noise is assumed. This is due to the factor that the shift register MPCG has no jitter accumulation from one clock phase to the other as in the DLL based MPCG. For N-phase clock generation, the shift register MPCG needs a reference clock with N times higher frequency and thus requires a VCO with higher frequency than the DLL counterpart. However, we can show that this does not lead to additional power consumption.

Advantages of Shift Registers Over DLLs for Flexible Low Jitter Multiphase Clock Generation

“…The simulated values fit the estimated curve well which means the threshold voltage mismatch dominates in this design. 4 If 50% reference clock duty cycle is guaranteed, both edges can be used.…”

“…For mismatch jitter, the DLL MPCG may have a slight advantage in some high-frequency cases. 4 From an implementation point of view, the SR MPCG has a simpler architecture since it does not require analog tuning and no feedback is needed. However, it can be more difficult to implement in applications where is large and is high since it works at , but this improves as technology advances.…”

“…This paper aims to make a solid comparison between these two MPCGs, primarily based on their power and absolute output jitter performance. A part of this work, related to thermal noise jitter was presented earlier in [4]. This paper also analyses deterministic jitter due to mismatch, and jitter transfer characteristics.…”

Components of Artificial Neural Networks Realized in CMOS Technology to be Used in Intelligent Sensors in Wireless Sensor Networks

“…The proposed multi-phase clock generator has been implemented inside the chip, to reduce the number of external pins of the chip. Circuits of this type are usually implemented using a chain of D-flip flops (DFFs) [27,28,29,30,31,32]. The advantage of such approach is the high immunity of the parameters of the clock to external conditions.…”

Low jitter low power phase locked loops using sub-sampling phase detection

“…Such clocks are for instance needed for time-interleaved ADCs and for image and harmonic rejection radio transceivers exploiting multiple clock phases. Two competing techniques to realize such clocks, one based on a shift register (SR) and the other on a DLL, are discussed [31], [32]. The relative merits of the two techniques are compared, primarily based on their jitter generation and power consumption.…”