We present a new analog-to-digital converter (ADC)-based architecture of a phase-tracking receiver (PT-RX) optimized for ultra-low-power (ULP) and ultra-low-voltage (ULV) operations for the Internet of Things (IoT). The RX employs a type-II loop configuration that offers improved stability compared with the previous type-I PT-RX solutions. In addition, the type-II loop is also very tolerant of long run-lengths of consecutive "1" or "0" symbol sequences. Fabricated in 28-nm CMOS, the prototype PT-RX targets Bluetooth low energy (BLE) standard consuming only 1.5 mW at a supply of ≤0.7 V. It maintains an adjacent-channel rejection (ACR) of ≥−11/3.5/17/27 dB at 0/±1/±2/±3 MHz offset and can tolerate out-of-band (OOB) blockers of minimum −21 dBm across 1.0-3.5 GHz while also offering a best-in-class figure of merit (FoM) of 181 dB, with a 1-Mb/s BLE sensitivity of −93 dBm. Index Terms-Bluetooth low energy (BLE), digitally controlled oscillator (DCO)-based receivers (RXs), discrete-time (DT) filter, Internet-of-Things (IoT), phase-tracking RXs (PT-RXs), successive-approximation-register (SAR)-analog-to-digital converter (ADC), ultra-low power (ULP), ultra-low voltage (ULV). I. INTRODUCTION T HE massive deployment of Internet-of-Things (IoT) applications calls for ultra-low-power (ULP) and ultralow-voltage (ULV) design techniques for system-on-chip (SoC) devices realized in nanoscale CMOS [1]-[4]. The RF receiver (RX) is a key IoT subsystem that takes a significant portion of the IoT's total power budget. In the industry, commercial RXs using Cartesian [i.e., in-phase/quadrature (I/Q)] topology [5], [6] aimed at Bluetooth low energy (BLE), a dominant standard in IoT devices, consume 5-10 mW. A more recent industry work [1], a superheterodyne discrete-time (DT) Cartesian RX, achieves the lowest power of 2.75 mW with a sensitivity of −95 dBm. However, it becomes more and more challenging to further reduce the power allocation for the RX,

The IC presented in this paper is a highly integrated low-power RF transceiver for wireless sensor networks (WSN) compliant with the IEEE 802.15.4 2.4GHz WPAN standard. It contains a radio controller with sleep timer and can perform higher-level MAC functions such as beacon detection and network timing synchronisation autonomously, thereby enabling significant power savings in the overall system. The primary design goal for the receive path is to achieve excellent channel selectivity and dynamic range combined with good sensitivity at very low power consumption, all of which are important parameters for the reliable operation of WSN in the harsh 2.4GHz ISM band. The receiver uses a direct-conversion architecture and offers up to 20dB improved interference rejection in the adjacent channels compared to recently published WPAN transceivers based on the low-IF architecture [1,2]. Further emphasizing WSN reliability, the receiver supports switched antenna diversity to mitigate multipath fading. Implemented in a 1P6M 0.18µm RFCMOS process, the IC occupies a die area of less than 5.9mm 2 . It operates with a supply voltage from 1.8V to 3.6V, draws 16.8mA in receive mode and 18mA when transmitting at 3dBm. Figure 24.4.1 shows the chip-level block diagram. The analog, VCO, synthesizer and digital sections are supplied by separate on-chip LDO regulators.Configuration data is retained in a 1.8V backup RAM, which is supplied by an ultra-low-power LDO. The radio controller is based on a power-and area-efficient custom MCU core with optimised instruction set. An amplitude-regulated 26MHz crystal oscillator acts as a calibration reference for the 32kHz RC oscillator. The transceiver is equipped with 2 differential RF ports. The 1 st port is an LNA input only. It has an LNA isolation switch (SW) to attenuate the input signal during the offset correction phase. The 2 nd port is shared between PA and LNA. The transmitter uses direct closed-loop VCO modulation through a fractional-N synthesizer. The bandwidth of the synthesizer is widened with a digital pre-emphasis filter, so that emissions and TX EVM specifications are met simultaneously. The VCO is running at twice the LO frequency to minimise LO self-mixing and pulling effects caused by interferers. The LNA is followed by a passive current-mode quadrature mixer. The input of each transimpedance amplifier (TIA) forms a summing node for the baseband side of the mixer switch pair and 2 current mode DACs which are part of the offset correction loop (OCL).A 3 rd -order 0.25dB-ripple Chebychev filter with 1.3MHz bandwidth attenuates interferers in the ADC sampling image at 13MHz by more than 65dB, and attenuates interferers in the adjacent channel at 5MHz offset by more than 40dB. A 3 rd -order digital IIR filter attenuates signals in the adjacent channel by an additional 35dB while maintaining an overall EVM of less than 5%. The PGA section provides 24dB of gain with 3dB steps and is followed by power-optimised 6b pipeline ADCs. The total voltage gain from antenna to the PGA output...

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Analog FIR filtering is proposed to improve the performance of a single stage gm-C channel selection filter for ultra low power Internet-of-Things receivers. The transconductor is implemented as a Digital-to-Analog Converter; allowing a varying transconductance in time, which results in a very sharp FIR filter. The filter is manufactured in 22 nm FDSOI and has a core area of 0.09 mm 2. It consumes 92 µW from a 700 mV supply and achieves f −60dB /f −3dB = 3.8. The filter has 31.5 dB gain, out-of-band OIP3 of 28 dBm and output referred 1-dB compression point of 3.7 dBm. The filter bandwidth is tunable from 0.06 to 3.4 MHz.

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High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4GHz ISM-band. In addition, low power consumption is very important for IoT receivers. We propose a 2.4GHz zero-IF receiver front-end architecture that reduces power consumption by 2× compared to state-of-the-art and improves selectivity by >20dB without compromising on other receiver metrics. To achieve this the entire receive chain is optimized. The LNTA is optimized to combine low noise with low power consumption. Stateof-the-art sub-30nm CMOS processes have almost equal strength complementary FETs, which result in altered design trade-offs. A Windmill 25%-duty cycle frequency divider architecture is proposed that uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog FIR filter is implemented to provide very high receiver selectivity with ultra low power consumption. The receiver front-end is fabricated in a 22nm FDSOI technology and has an active area of 0.5mm 2 . It consumes 370µW from a 700mV supply voltage. This low power consumption is combined with 5.5dB noise figure. The receiver front-end has -7.5dBm IIP3 and 1-dB gain compression for a -22dBm blocker; both at maximum gain of 61dB. From three channels offset onward the adjacent channel rejection is ≥63dB for BLE, BT5.0 and IEEE802.15.4.

Analog FIR filtering is proposed to improve the performance of a single stage gm-C channel selection filter for ultra low power Internet-of-Things receivers. The transconductor is implemented as a Digital-to-Analog Converter; allowing a varying transconductance in time, which results in a very sharp FIR filter. The filter is manufactured in 22 nm FDSOI and has a core area of 0.09 mm 2 . It consumes 92 µW from a 700 mV supply and achieves f −60dB /f −3dB = 3.8. The filter has 31.5 dB gain, out-of-band OIP3 of 28 dBm and output referred 1-dB compression point of 3.7 dBm. The filter bandwidth is tunable from 0.06 to 3.4 MHz.

We present an architecture of a Bluetooth low energy (BLE)-compliant receiver which, for the first time ever, breaks the 1 mW barrier of power consumption. It is based on a type-II phase-tracking loop and addresses the mutual magnetic coupling between on-chip inductors of a digitally controller oscillator (DCO) and low-noise transconductance amplifier (LNTA), which causes RX performance degradation in the priorart implementations. An inverter-based inductor-free LNTA is employed instead. The resulting adjacent channel rejection (ACR) improves by 1.5/2.5 dB at 2/3 MHz offset. By further leveraging current-reuse and switched-capacitor circuitry, this RX achieves the best-in-class FoM of 183.2 dB with sensitivity of −93.2 dBm. Thanks to the single-channel topology, the proposed RX occupies tiny area of 0.48 mm 2 in 28-nm CMOS. Index Terms-Bluetooth low energy (BLE) receivers (RXs), digitally controlled oscillator (DCO)-based receivers, discretetime (DT) receivers, Internet-of-Things (IoT), phase-tracking RXs (PT-RXs), inverter-based RXs, current-reuse, ultra-low power (ULP), ultra-low voltage (ULV).