A 0.06–3.4-MHz 92-μW Analog FIR Channel Selection Filter With Very Sharp Transition Band for IoT Receivers

IEEE J. Solid-State Circuits

et al. 2021

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High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4GHz ISM-band. In addition, low power consumption is very important for IoT receivers. We propose a 2.4GHz zero-IF receiver front-end architecture that reduces power consumption by 2× compared to state-of-the-art and improves selectivity by >20dB without compromising on other receiver metrics. To achieve this the entire receive chain is optimized. The LNTA is optimized to combine low noise with low power consumption. Stateof-the-art sub-30nm CMOS processes have almost equal strength complementary FETs, which result in altered design trade-offs. A Windmill 25%-duty cycle frequency divider architecture is proposed that uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog FIR filter is implemented to provide very high receiver selectivity with ultra low power consumption. The receiver front-end is fabricated in a 22nm FDSOI technology and has an active area of 0.5mm 2 . It consumes 370µW from a 700mV supply voltage. This low power consumption is combined with 5.5dB noise figure. The receiver front-end has -7.5dBm IIP3 and 1-dB gain compression for a -22dBm blocker; both at maximum gain of 61dB. From three channels offset onward the adjacent channel rejection is ≥63dB for BLE, BT5.0 and IEEE802.15.4.

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Section: Baseband Analog Fir Filtermentioning

confidence: 99%

2.4-GHz Highly Selective IoT Receiver Front End With Power Optimized LNTA, Frequency Divider, and Baseband Analog FIR Filter

IEEE J. Solid-State Circuits

et al. 2021

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“…using analog FIR or Filtering-by-Aliasing [7] -have very high power consumption, not suitable for IoT applications. A recent Analog Finite-Impulse-Response (AFIR) filter [8] shows promising results to improve channel filtering. [8] uses a much lower FIR update rate than [7] to considerably reduce power consumption.…”

mentioning

confidence: 99%

“…A recent Analog Finite-Impulse-Response (AFIR) filter [8] shows promising results to improve channel filtering. [8] uses a much lower FIR update rate than [7] to considerably reduce power consumption. This comes at the cost of a filter alias, but the inherent windowed integration sinc filtering mitigates this filter alias.…”

mentioning

confidence: 99%

“…All filtering -including channel filtering -is performed in the analog domain, which significantly reduces the dynamic range and sampling rate requirements on the subsequent Analog-to-Digital Converter (ADC). [8]. A 10bit transconductor Digital-to-Analog Converter (gmDAC) is varied over time according to the FIR coefficients stored in the memory.…”

mentioning

confidence: 99%

“…The output common mode of the gmDAC is set by a common mode feedback (CMFB) circuit. The gmDAC is 5bit thermometer coded and 5bit binary coded for reduced mismatch and control logic power consumption [8]. The FIR code is provided at 16MHz/32MHz (1Mbps/2Mbps) -resulting in filter aliases at integer multiples of 16MHz/32MHz.…”

mentioning

confidence: 99%

See 2 more Smart Citations

30.4 A 370µW 5.5dB-NF BLE/BT5.0/IEEE 802.15.4-Compliant Receiver with >63dB Adjacent Channel Rejection at >2 Channels Offset in 22nm FDSOI

2020 IEEE International Solid- State Circuits Conference - (ISSCC)

et al. 2020

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Low-Power Highly Selective Channel Filtering Using a Transconductor–Capacitor Analog FIR

IEEE J. Solid-State Circuits

et al. 2020

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