Analog FIR filtering is proposed to improve the performance of a single stage gm-C channel selection filter for ultra low power Internet-of-Things receivers. The transconductor is implemented as a Digital-to-Analog Converter; allowing a varying transconductance in time, which results in a very sharp FIR filter. The filter is manufactured in 22 nm FDSOI and has a core area of 0.09 mm 2. It consumes 92 µW from a 700 mV supply and achieves f −60dB /f −3dB = 3.8. The filter has 31.5 dB gain, out-of-band OIP3 of 28 dBm and output referred 1-dB compression point of 3.7 dBm. The filter bandwidth is tunable from 0.06 to 3.4 MHz.
High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4GHz ISM-band. In addition, low power consumption is very important for IoT receivers. We propose a 2.4GHz zero-IF receiver front-end architecture that reduces power consumption by 2× compared to state-of-the-art and improves selectivity by >20dB without compromising on other receiver metrics. To achieve this the entire receive chain is optimized. The LNTA is optimized to combine low noise with low power consumption. Stateof-the-art sub-30nm CMOS processes have almost equal strength complementary FETs, which result in altered design trade-offs. A Windmill 25%-duty cycle frequency divider architecture is proposed that uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog FIR filter is implemented to provide very high receiver selectivity with ultra low power consumption. The receiver front-end is fabricated in a 22nm FDSOI technology and has an active area of 0.5mm 2 . It consumes 370µW from a 700mV supply voltage. This low power consumption is combined with 5.5dB noise figure. The receiver front-end has -7.5dBm IIP3 and 1-dB gain compression for a -22dBm blocker; both at maximum gain of 61dB. From three channels offset onward the adjacent channel rejection is ≥63dB for BLE, BT5.0 and IEEE802.15.4.
Analog FIR filtering is proposed to improve the performance of a single stage gm-C channel selection filter for ultra low power Internet-of-Things receivers. The transconductor is implemented as a Digital-to-Analog Converter; allowing a varying transconductance in time, which results in a very sharp FIR filter. The filter is manufactured in 22 nm FDSOI and has a core area of 0.09 mm 2 . It consumes 92 µW from a 700 mV supply and achieves f −60dB /f −3dB = 3.8. The filter has 31.5 dB gain, out-of-band OIP3 of 28 dBm and output referred 1-dB compression point of 3.7 dBm. The filter bandwidth is tunable from 0.06 to 3.4 MHz.
Analog Finite-Impulse-Response (AFIR) filtering is proposed to realize low power channel selection filters for Internet-of-Things receivers. High selectivity is achieved using an architecture based on only a single -time-varyingtransconductance and integration capacitor. The transconductance is implemented as a Digital-to-Analog Converter and is programmable by an on-chip memory. The AFIR operating principle is shown step-by-step, including its complete transfer function with aliasing. The filter bandwidth and transfer function are highly programmable through the transconductance coefficients and clock frequency. Moreover, the transconductance programmability allows an almost ideal filter response to be realized by careful analysis and compensation of the parasitic circuit impairments. The filter, manufactured in 22nm FDSOI, has an active area of 0.09mm 2 . Its bandwidth can be accurately tuned from 0.06 to 3.4MHz. The filter consumes 92µW from a 700mV supply. This low power consumption is combined with a high selectivity: f -60dB /f -3dB =3.8. The filter has 31.5dB gain and 12nV/ √ Hz input-referred noise for a 0.43MHz bandwidth. The OIP3 is 28dBm, independent of the frequency offset. The outputreferred 1dB-compression point is 3.7dBm, and the in-band gain compresses by 1dB for an -3.7dBm out-of-band input signal, while still providing >60dB of filtering.
This paper presents a feedforward phase noise cancellation technique to reduce phase noise of the output clock signal of a phase-locked loop (PLL). It uses a sub-sampling phase detector to measure the phase noise and a variable time delay for cancellation. Both phase noise and spurs are reduced. Analytical expressions have been derived that characterize the performance of this technique and show its fundamental limitations. A subsampling phase-locked loop with the cancellation technique as a built-in feature is described. The feedforward technique has no stability requirements in contrast to conventional PLL architectures. The phase noise reduction bandwidth is increased to almost a third of the reference frequency-3x the maximal bandwidth for 3 rd order type-II PLLs. The proposed analytical model shows a phase noise reduction of 9 dB at a frequency offset of f ref /10. The total rms jitter is improved by 7.2 dB. The analytical results are verified by simulations.
IoT Receiver Techniques On Filtering, Power Consumption and Phase Noise Proefschrift ter verkrijging van de graad van doctor aan de Universiteit Twente, op gezag van de rector magnificus, prof. dr. ir. A. Veldkamp, volgens besluit van het College voor Promoties in het openbaar te verdedigen op woensdag 7 april 2021 om 14:45 uur door Bartholomeus Jacobus Thijssen geboren op 25 oktober 1992 te Ede Dit proefschrift is goedgekeurd door: de promotor prof. dr. ir. B. Nauta de co-promotor dr. ing. E.A
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