A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Bae, Seung-Jun; Sohn, Young-Soo; Oh, Taehyoun; Kim, Sihong; Yang, Yongheng; Kim, Dae-Hyun; Kwak, Sang-Hyup; Seol, Hoseok; Shin, Chang-Ho; Park, Min Sang; Han, Gong-Heom; Kim, Byeong-Cheol; Cho, Yong-Ki; Kim, Hye‐Ran; Doo, Su-Yeon; Kim, Young‐Sik; Kang, Dongseok; Choi, YoungRok; Bang, Sam-Young; Park, Sunyoung; Shin, Yong-Jae; Moon, Gil-Shin; Park, Cheol-Goo; Kim, Woo-Seop; Yang, Hyang-Ja; Lim, Jeong-Don; Park, Kwang-Il; Choi, Jongwan; Jun, Young-Hyun

doi:10.1109/isscc.2011.5746414

Cited by 21 publications

(8 citation statements)

References 3 publications

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“…Depending on target applications (e.g. graphics [8] and mobile [22,33]), the designs of the I/O interfaces, the widths of the global datalines, or the transistor characteristics are modified, whereas the internal organization is mostly unchanged, as illustrated in Figure 3.…”

Section: Modern Dram Device Organizationmentioning

confidence: 99%

Reducing memory access latency with asymmetric DRAM bank organizations

Son

Seongil

et al. 2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

103

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DRAM has been a de facto standard for main memory, and advances in process technology have led to a rapid increase in its capacity and bandwidth. In contrast, its random access latency has remained relatively stagnant, as it is still around 100 CPU clock cycles. Modern computer systems rely on caches or other latency tolerance techniques to lower the average access latency. However, not all applications have ample parallelism or locality that would help hide or reduce the latency. Moreover, applications' demands for memory space continue to grow, while the capacity gap between lastlevel caches and main memory is unlikely to shrink. Consequently, reducing the main-memory latency is important for application performance. Unfortunately, previous proposals have not adequately addressed this problem, as they have focused only on improving the bandwidth and capacity or reduced the latency at the cost of significant area overhead.We propose asymmetric DRAM bank organizations to reduce the average main-memory access latency. We first analyze the access and cycle times of a modern DRAM device to identify key delay components for latency reduction. Then we reorganize a subset of DRAM banks to reduce their access and cycle times by half with low area overhead. By synergistically combining these reorganized DRAM banks with support for non-uniform bank accesses, we introduce a novel DRAM bank organization with center high-aspect-ratio mats called CHARM. Experiments on a simulated chip-multiprocessor system show that CHARM improves both the instructions per cycle and system-wide energy-delay product up to 21% and 32%, respectively, with only a 3% increase in die area. Figure 1: The capacity and bandwidth of DRAM devices have increased rapidly over time, but their latency has decreased much more slowly [41].

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Section: Modern Dram Device Organizationmentioning

confidence: 99%

Reducing memory access latency with asymmetric DRAM bank organizations

Son

Seongil

et al. 2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

103

View full text Add to dashboard Cite

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“…The existing literature on 2.5D die‐to‐die IOs can be considered scarce and post‐silicon results of the employed approaches are rarely available. Therefore, relevant IO design topologies must be imported in the design space from off‐chip and on‐chip signaling, which are currently pushing into multi‐Gbps range on a single wire . For multi‐Gbps off‐chip transmission with a low energy/bit, low voltage differential mode (LVDS) signaling or current‐mode signaling is preferred, which possess faster data rate, better energy efficiency because of reduced signal swing on the wire and common‐mode noise immunity with the cost of doubling the pin‐count and routes on the interposer.…”

Section: Introductionmentioning

confidence: 99%

IO circuit design for 2.5D through‐silicon‐interposer interconnects

Jawed

Afridi

Anjum

et al. 2016

Circuit Theory & Apps

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This paper presents four topologies of voltage-mode un-terminated IO cells in 28-nm CMOS for singleended rail-to-rail signaling over a passive interposer die in 2.5D configuration for >1Gbps data rates. The presented design explores the existing IO design-space from a 2.5D viewpoint, optimizing existing topologies from area, speed, power and protection perspectives, with a higher degree of configurability in the form of pre-emphasis and slew-rate control. The transmitter (TX) embeds pre-emphasis to enhance high-frequency components of the signal for longer low-pass natured channels. The TX also implements slew-rate control to minimize reflections on shorter channels because of impedance discontinuities and also to minimize simultaneous switching noise. Level-shifting capability embedded in the receiver (RX) enables multi-technology interfacing where different dies are signaling at their core voltages (range: 0.7 V-1.8 V) instead of following a particular signaling standard. The measurement results of the transceivers, over a interposer of length of 3.5 mm, demonstrate ±5% duty-cycle distortion with 700 μW at 500 MHz/0.8-V-signaling on the channel with jitter of 20 ps, ±10% duty-cycle distortion with 1.8 mW at 1Gbps/0.9-V signaling with jitter of 20 ps, ±10% duty-cycle distortion with 2 mW at 2Gbps/0.7-V signaling for 1-V receiver core voltage with a jitter of 10 ps. of limiter material or functional errors because of electro-thermal coupling or excessive leakage currents which can form a positive feedback loop with the temperature leading to thermal run-away problem [10,11]. Moreover, the thermal expansion coefficients of TSV material and substrate are different, which can result in large temperature induced mechanical stress again leading to nonuniform distribution of delay across the area [5].Recently, 2.5D IC stacking has emerged as a viable alternative because of its higher mechanical and thermal reliability with a comparable interconnect density [10,12,13]. Several flip-chip dies are attached with fine-pitch micro-bumps to a single passive interposer die also known as throughsilicon-interposer (TSI) communication. This interposer die allows connections between adjacently placed multi-technology dies as well as connections to the package, providing low interconnect delay, high-bandwidth, multi-technology interfacing and reduced ESD protection requirements for die-to-die connections [14]. Moreover, although incurring the cost of adding a passive Si interposer, TSI avoids the issues faced by TSV based 3D configuration related to the high-temperature gradients because of poor thermal distribution, difficult IO planning, large keep-out areas and reliable manufacturing [10,13,15,16]. When compared with traditional backplane through-PCB interconnections which span lengths of few inches (>25 cm), TSI interconnects are much shorter (few mm) in length [2], which is one of the main reasons for their enhanced performance. For example, at 5 Gbps a 25-cm-long PCB track suffers from approximately 20-dB additional channel l...

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“…Traditional DRAM transmitters have used push-pull type drivers like [3] and [4], but, similar to rail to rail CMOS driver of [1] and [2], these drivers are not proper to low power operation at high speed. To achieve low power operation, the LPDDR4 DRAM uses n over n driver with VSSQ termination as shown in [5] and [6].…”

Section: Introductionmentioning

confidence: 99%

A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel

Lee

Song

Byeon

et al. 2015

IEEE J. Solid-State Circuits

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A 16.8 Gbps/channel single-ended transceiver for SiP-based DRAM interface on silicon carrier channel is proposed in this paper. A transmitter, receiver, and channel are all included in a single package as SiP. A current mode 4:1 MUX with 1-tap feed-forward equalizer (FFE) is used as a serializer, and this 4:1 MUX uses 25% duty clock to prevent short circuit current when consecutive 2-phase clocks overlap. Additionally, an open drain output driver with asynchronous type 1-tap FFE is used in the transmitter. Because of its small physical size, a common mode variation of Si-carrier channel from process variation is more serious than that of conventional PCB. This common mode variation degrades bit error rates (BER) at single-ended signaling. To obtain effective single-ended signaling on Si-carrier channel, a source follower-based continuous time linear equalizers and selfgenerator with training algorithm on the receiver are proposed. An implemented Si-carrier channel uses meshed layer as a reference to reduce insertion loss. A BER less than 1e-12 is achieved in 65 nm CMOS and the power efficiency of the transceiver is 5.9 pJ/bit with 120 terminations at each transceiver side.Index Terms-Bit error rates (BER) and 120 terminations, continuous time linear equalizer (CTLE), feed-forward equalizer (FFE), selfgenerator, single-ended transceiver, SiP-based DRAM interface.

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A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Cited by 21 publications

References 3 publications

Reducing memory access latency with asymmetric DRAM bank organizations

Reducing memory access latency with asymmetric DRAM bank organizations

IO circuit design for 2.5D through‐silicon‐interposer interconnects

A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel

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