Reducing memory access latency with asymmetric DRAM bank organizations

Son, Young Hoon; Seongil, O; Ro, Yuhwan; Lee, Jae Woo; Ahn, Jung Ho

doi:10.1145/2485922.2485955

Cited by 103 publications

(70 citation statements)

References 60 publications

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“…We deal with three types of in-DRAM cache structures based on recently published tiered-latency DRAM (TL-DRAM) and center high-aspect-ratio mats (CHARM) [19,20]. TL-DRAM: This divides the bit line of the DRAM array into two segments and uses the long one as the DRAM memory, and the short one as the in-DRAM cache [19,21].…”

Section: Background and In-dynamic Random Access Memory (Dram) Cacmentioning

confidence: 99%

“…The in-DRAM cache can be implemented as SRAM or DRAM, but only the DRAM is covered in this paper. This architecture has the advantage of being able to implement a significant amount of cache capacity, but it has the disadvantage of requiring a large area overhead.Cache-bank: This is similar to the CHARM structure [20]. Some DRAM banks are used as low-latency DRAM caches, and this paper calls them cache banks (Figure 3c).…”

Section: Background and In-dynamic Random Access Memory (Dram) Cacmentioning

confidence: 99%

“…Cache-bank: This is similar to the CHARM structure [20]. Some DRAM banks are used as low-latency DRAM caches, and this paper calls them cache banks (Figure 3c).…”

Section: Background and In-dynamic Random Access Memory (Dram) Cacmentioning

confidence: 99%

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In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs

Shin

Chung

2019

Micromachines

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Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache management techniques and latency hiding schemes to reduce DRAM access time, in a high-performance system using high-capacity 3D-stacked DRAM, it is ultimately essential to reduce the latency of the DRAM itself. To solve this problem, various asymmetric in-DRAM cache structures have recently been proposed, which are more attractive for high-capacity DRAMs because they can be implemented at a lower cost in 3D-stacked DRAMs. However, most research mainly focuses on the architecture of the in-DRAM cache itself and does not pay much attention to proper management methods. In this paper, we propose two new management algorithms for the in-DRAM caches to achieve a low-latency and low-power 3D-stacked DRAM device. Through the computing system simulation, we demonstrate the improvement of energy delay product up to 67%.

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Section: Background and In-dynamic Random Access Memory (Dram) Cacmentioning

confidence: 99%

Section: Background and In-dynamic Random Access Memory (Dram) Cacmentioning

confidence: 99%

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In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs

Shin

Chung

2019

Micromachines

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“…Asymmetric DRAM bank organizations for reducing the average main-memory access latency were proposed in [7]. Thus, memory subsystems that can support such applications have become a key issue in SoC designs.…”

Section: Previous Workmentioning

confidence: 99%

WARP: Memory Subsystem Effective for Wrapping Bursts of a Cache

Jang

2017

ETRI Journal

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State‐of‐the‐art processors require increasingly complicated memory services for high performance and low power consumption. In particular, they request transfers within a burst in a wrap‐around order to minimize the miss penalty of a cache. However, synchronous dynamic random access memories (SDRAMs) do not always generate transfers in the wrap‐round order required by the processors. Thus, a memory subsystem rearranges the SDRAM transfers in the wrap‐around order, but the rearrangement process may increase memory latency and waste the bandwidth of on‐chip interconnects. In this paper, we present a memory subsystem that is effective for the wrapping bursts of a cache. The proposed memory subsystem makes SDRAMs generate transfers in an intermediate order, where the transfers are rearranged in the wrap‐around order with minimal penalties. Then, the transfers are delivered with priority, depending on the program locality in space. Experimental results showed that the proposed memory subsystem minimizes the memory performance loss resulting from wrapping bursts and, thus, improves program execution time.

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“…As memory technology scales to higher densities, for example, 16Gb DRAM device that has been defined in DDR4 SDRAM standard [2], performance degradation and energy consumption that attributes to refresh grow from negligible to severe. Currently refresh overhead has become the biggest restriction for DRAM scalability, making it increasingly important to reduce refresh overhead [3].…”

Section: Introductionmentioning

confidence: 99%

Alleviating DRAM Refresh Overhead Via Inter-rank Piggyback Caching

Guo

Huang

Young

et al. 2015

2015 IEEE 23rd International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems

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DRAM cells leak charge over time, causing stored data to be lost. Therefore, periodic refreshes are required to ensure data integrity. Modern DRAM usually refreshes cells at rank level, resulting in an entire rank being unavailable during a refresh period. As DRAM density keeps increasing, more rows need to be refreshed during a single refresh operation, which causes higher refresh latency and significantly degrades the overall memory system performance.To mitigate DRAM refresh overhead, we propose a caching scheme, called Rank-level Piggyback Caching, or RPC for short, based on the fact that ranks in the same channel are refreshed in a staggered manner. The key idea is to cache the to-be-read data in a rank (e.g. Rank 1) to its adjacent rank (e.g. Rank 2) before Rank 1 is locked for refresh. Each rank reserves or over-provisions a very small area, denoted as a cache region, to store the cached data. The cache regions from all ranks are organized in a rotated fashion. In other words, the cached data for the last rank is stored in the first rank. When a read request arrives at a rank undergoing refresh, the memory controller first checks the cache region in the next rank in the same channel; if the requested data is cached, the memory controller services the request from the cache without waiting for the refresh operation to complete, which reduces memory access latency and improves system performance.Our experimental results show that RPC outperforms existing Fine Granularity Refresh modes. In a single-core and four-rank system, it improves system performance by 8.7% and 10.8% on average for the PARSEC 2.1 and SPLASH-2 benchmark suites, respectively. In a four-core and four-rank system, the improvement of system performance for these two benchmark suites is 8.6% and 12.2%, respectively.

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Reducing memory access latency with asymmetric DRAM bank organizations

Cited by 103 publications

References 60 publications

In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs

In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs

WARP: Memory Subsystem Effective for Wrapping Bursts of a Cache

Alleviating DRAM Refresh Overhead Via Inter-rank Piggyback Caching

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