In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs

Abstract

Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache management techniques and latency hiding schemes to reduce DRAM access time, in a high-performance system using high-capacity 3D-stacked DRAM, it is ultimately essential to reduce the latency of the DRAM itself. To solve this problem, various asymmetric in-DRAM cache structures have recently been proposed, which are more attractive for high-capacity DRAMs because they can be implemented at a lower cost in 3D-stacked DRAMs. However, most research mainly focuses on the architecture of the in-DRAM cache itself and does not pay much attention to proper management methods. In this paper, we propose two new management algorithms for the in-DRAM caches to achieve a low-latency and low-power 3D-stacked DRAM device. Through the computing system simulation, we demonstrate the improvement of energy delay product up to 67%.

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

“…ror models 4 ⃝ based on a previous understanding of DRAM errors (e.g., from past experiments or scientific studies). Examples of such error models include: analytical models based on understanding DRAM failure modes (e.g., sources of runtime faults [51,60,149,[371][372][373]), parametric statistical models that provide useful summary statistics (e.g., lognormal distribution of cell data-retention times [276,277,[374][375][376][377][378][379][380], exponential distribution of the time-in-state of cells susceptible to variable-retention time (VRT) [65,94,150,166,367,[381][382][383][384][385][386][387][388][389]), physics-based simulation models (e.g., TCAD [232,374,[390][391][392] and SPICE models [14,59,78,106,109,283,[393][394][395]), and empirically-determined curves that predict observations well (e.g., single-bit error rates…”

Power and thermal management in SRAM and DRAM using adaptive body biasing technique

“…H. Shin, and E. Chung in [5] proposed two management algorithms for in-DRAM caches in order to achieve low-latency and low-power 3D-stacked DRAM device. Through the computing system simulation, the improvements of energy delay product were higher than 67%.…”

Editorial for the Special Issue on Emerging Memory and Computing Devices in the Era of Intelligent Machines

“…These range from material-and cell-level studies (X. Lian et al [4]; Z. Shen et al [5]; C. Xie et al [6]; and K. Drake et al [7]), to the applications of RRAM in processing of biosignals (Y. K. Lee et al [8]), neural networks (S. Jo et al [9]; and S. N. Truong [10]), and nonvolatile processors (X. Xue et al [11]). (iii) Several of the selected articles discuss new computing paradigms that may take advantage of emerging memory devices (G. Santoro et al [12] and S. Nam et al [13]), as well as extensions, modifications, or innovations in existing volatile and nonvolatile memory technologies (at both the device and circuit levels), which may add new functionalities or improve their performance for computing applications (H. H. Shin et al [14]; S. Yang et al [15]; A. Subbiah and T. Ogunfunmi [16]; H. E. Yantir et al [17]; and L. Gan et al [18]). Finally, in "Development of Bioelectronic Devices Using Bionanohybrid Materials for Biocomputation System," J. Yoon et al [19] review their recent progress in the development of biocompatible memory and computing devices.…”