WARP: Memory Subsystem Effective for Wrapping Bursts of a Cache

Abstract

State‐of‐the‐art processors require increasingly complicated memory services for high performance and low power consumption. In particular, they request transfers within a burst in a wrap‐around order to minimize the miss penalty of a cache. However, synchronous dynamic random access memories (SDRAMs) do not always generate transfers in the wrap‐round order required by the processors. Thus, a memory subsystem rearranges the SDRAM transfers in the wrap‐around order, but the rearrangement process may increase memory latency and waste the bandwidth of on‐chip interconnects. In this paper, we present a memory subsystem that is effective for the wrapping bursts of a cache. The proposed memory subsystem makes SDRAMs generate transfers in an intermediate order, where the transfers are rearranged in the wrap‐around order with minimal penalties. Then, the transfers are delivered with priority, depending on the program locality in space. Experimental results showed that the proposed memory subsystem minimizes the memory performance loss resulting from wrapping bursts and, thus, improves program execution time.