A 2.5 Gbps - 3.125 Gbps multi-core serial-link transceiver in 0.13 μm CMOS

Geurts, T.; Rens, W.; Crols, Jan; Kashiwakura, S.; Segawa, Y.

doi:10.1109/esscir.2004.1356725

Cited by 13 publications

(8 citation statements)

References 4 publications

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“…SIMULATION RESULTS AND CONCLUSIONS The proposed 16Gbps SerDes architecture was implemented in a TSMC 65nm technology and simulated at a supply voltage of 1V. The total power consumed in the Tx/Rx pair with the transmission line was 18.1mW at the TT corner and 105C, which is smaller than the power dissipation of similar published signaling architectures [2] and [3]. Table 1 shows the power consumption in each block of the design, and Table 2 shows a comparison between this work and [1].…”

Section: Inverter Switching Threshold Caliberationmentioning

confidence: 98%

“…Table 1 shows the power consumption in each block of the design, and Table 2 shows a comparison between this work and [1]. SerDes architecture proposed in this work and in [1] consumes very small power as compared to other work [2] and [3]. This results from using a self timed three-level encoding scheme that enables recovering the clock from the data, without the need for an extra clock link or using power hungry complex blocks, such as PLLs and CDRs.…”

Section: Inverter Switching Threshold Caliberationmentioning

confidence: 99%

“…Since, interconnects no longer scale with the technology, parallel buses can occupy a large area as compared to the processing elements which results in wiring complexity and routing congestion. A promising solution is replacing the parallel bus with serial links using a SerDes transceiver [1], [2], and [3]. Serial links have been used for decades in off-chip communication between ICs, due to the limited number of I/O pins.…”

Section: Introductionmentioning

confidence: 99%

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A 16Gbps low power self-timed SerDes transceiver for multi-core communication

Hussein

Safwat

Ghoneima

et al. 2012

2012 IEEE International Symposium on Circuits and Systems

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This paper presents a modified design for a self-timed SerDes transceiver that was recently published [1]. The new architecture overcomes the main problems that arise in [1], while offering the same advantages. Resistive termination is used instead of source matching to eliminate the need for Manchester coding in [1], this resistive termination increased the data rate to be 16Gbps compared to 12Gbps in [1]. Moreover, resistive termination removed the limitation on the minimum operating frequency that existed in [1], solving a lot of problems at the slow process corners. A single ended transmission line is used instead of the differential transmission line in [1]. A calibration circuit is implemented to control the switching threshold of the detector at the receiver side to account for voltage and process variations. The SerDes transceiver is implemented for a 3mm long on-chip transmission line in 65nm TSMC CMOS technology, which is the same as [1]. The total power consumed in the Tx/Rx pair with the transmission line is 18.1mWatt, compared to 15.5mWatt in [1]. The proposed architecture have the same advantages in [1] of being self timed, eliminating the need for complex power hungry blocks such as Clock and Data Recovery (CDR) at the receiver, and being insensitive to jitter accumulated during transmission.

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Section: Inverter Switching Threshold Caliberationmentioning

confidence: 98%

Section: Inverter Switching Threshold Caliberationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 16Gbps low power self-timed SerDes transceiver for multi-core communication

Hussein

Safwat

Ghoneima

et al. 2012

2012 IEEE International Symposium on Circuits and Systems

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“…The need for such precision quadrature clock signals traverses multiple standards in both wireline and wireless transceivers and also extends to oversampling ADCs and clocking signals for DRAM, CPUs, etc. In many applications such as a multi-lane, multi-Gb/s link, there is a need for local generation of quadrature clock signals from the high-speed differential clock distributed across multiple channels [1]. The quadrature clock phases then drive the phase-detectors or phase-interpolators in the clock and data recovery (CDR) unit, to generate the sampling clock for the incoming data.…”

Section: Introductionmentioning

confidence: 99%

A Phase-Interpolation and Quadrature-Generation Method Using Parametric Energy Transfer in CMOS

Bhardwaj

Lee

2015

IEEE Trans. Circuits Syst. I

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This work focuses on generation of quadrature clocks with high phase accuracy and low noise, while reducing area and power consumption. The design objective is to make these quadrature oscillators suitable for applications in power-and area-constrained SOCs. We demonstrate in this work quadrature clock generation using parametric capacitance modulation in CMOS technology. We present a quadrature-generation method that is based on parametric energy transfer to an LC resonator. The phase-sensitive nature of parametric pumping is used to generate a signal in quadrature with an incoming clock signal. The design also provides the capability of phase interpolation about quadrature, which is useful in many applications. The detailed system implementation is demonstrated and experimentally verified through a prototype in 65 nm CMOS.

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“…A clock multiplier is one of the very important components of SerDes system. In conventional high-speed SerDes systems like [8], [10], 0 and [5], to achieve maximum bandwidth and pack large number of parallel data lines to one serial link, low-jitter fast-locking PLL based clock multipliers/frequency synthesizers are used to drive the parallel to serial converters. Similarly a clock recovery circuit, on the receiver side, employs sophisticated PLLs or DLLs to recover the clock on the receiver end to capture and deserialize data back to a parallel form.…”

Section: Introductionmentioning

confidence: 99%

2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology

Bhatti

Denneau

Draper

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

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This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as compared to conventional SerDes Designs, making it very attractive for modest budget multi-core and multi-processor ASICs with wide communication buses that are difficult to accommodate within the pin count of commonly available packaging. The design employs a "Statistical Random Sampling Technique" to observe and adjust the synchronization and serialization signals at start up rather than using a resource-heavy PLL or DLL based frequency multiplier/synthesizer and clock data recovery circuits. The serialization and deserialization logic is based on standard cell technology that makes the design highly portable. Multiple serial lines are bundled with a strobe that is used as a reference signal for deserialization. Data-to-strobe timing skew is compensated by adjusting the launch times of strobe and data symbols at the sender side. The edges of the strobe are set within the eye of data symbols to have maximum timing margin, which makes the design inherently tolerant of jitter. Power consumption of the proposed SerDes design is 30 mW per serial link targeted to IBM Cu-11(130 nm) Technology, nearly a 2.5x improvement over the conventional design with a 60% less area requirement. Categories and Subject Descriptors General TermsMeasurement, Design and Theory.

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A 2.5 Gbps - 3.125 Gbps multi-core serial-link transceiver in 0.13 μm CMOS

Cited by 13 publications

References 4 publications

A 16Gbps low power self-timed SerDes transceiver for multi-core communication

A 16Gbps low power self-timed SerDes transceiver for multi-core communication

A Phase-Interpolation and Quadrature-Generation Method Using Parametric Energy Transfer in CMOS

2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology

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