Abstract-A specific value of duty cycle of an on-chip clock or signal often becomes of extreme significance in VLSI circuits like DRAM's, dynamic/domino pipelined circuits, pipelined analog-to-digital converters (ADC) and Serializer / Deserializer (SERDES) circuits, which are sensitive to the duty cycle or where operations are synchronized with both transitions of the clock. This paper introduces a novel idea based on a random sampling technique of inferential statistics for measurement and local correction of the duty cycle of high-speed on-chip signals. The high measurement accuracy achievable through the proposed random sampling technique provides a way to correct the duty cycle with a maximum error of less than half the smallest delay resolution unit available for correction. An input signal with duty cycle from 30% to 70% can be adjusted to a wide range of values within this range using a purely digital, area-efficient standard cell based design. Our experimental results gathered though extensive simulations of the proposed circuit manifest a very close correlation to the expected theoretical results.
Abstract-This paper introduces a technique to measure and adjust the relative phase of on-chip high speed digital signals using a random sampling technique of inferential statistics. The proposed technique as applied to timing uncertainty mitigation in the signaling of a digital system is presented as an example; the relative phase information is used to minimize the timing skew. The proposed circuit captures the state of the signals under measurement simultaneously at random instants of time and gathers a large sample data to estimate the relative phase between the signals. By carefully premeditating the sample size, the accuracy and confidence of the result can be set to a level as high as desired. Accurately sensed value of relative phase enables the correction circuit to reduce the maximum correction error, less than half the maximum delay resolution unit available for adjustment. A pure standard cell based circuit design approach is used that reduces the overall design time and circuit complexity. The test results of the proposed circuit manifest a very close correlation to the simulated and theoretically expected results. The random sampling unit (RSU) circuit proposed for phase measurement in this paper occupies 3350 (µm) 2 area in 130nm technology, which is an order of magnitude smaller than what is required for its analog equivalent in the same technology.
As technology scales down at an exponential rate, leakage power is fast becoming the dominant component of the total power budget. A large share of the total leakage power is dissipated in the cache hierarchy. To reduce cache leakage, individual cache lines can be kept in drowsy mode, a low voltage, low leakage state. Every cache access may then result in dynamic power consumption and performance penalties. A trade-off between the amount of leakage power saved on one hand, and the impact on dynamic power and performance on the other hand must be reached.To affect this trade-off, we introduce "slumberous caches" in which the power level of cache lines is controlled with the cache replacement policy. In a slumberous cache, cache lines are maintained at different power save modes which we call "tranquility levels", which depend on their order of replacement priorities.We evaluate the trade-offs in the context of PLRU, a common cache replacement algorithm. We explore various assignments of the tranquility levels to lines and compare overall power and performance impacts. As technology scales down, the dynamic power required to energize slumberous cache lines drops drastically while the leakage power savings remain roughly steady. The performance penalty--in cycles--remains constant with technology scaling for each scheme we evaluate.
Abstract-A statistical random sampling technique has recently emerged as an elegant design-time efficient technique to address many timing issues of on-chip signals. To obtain reliable measurement results, it requires uniformly distributed sampling edges within the interval defined by the periodic cycles of the signal under measurement. This paper analyzes the characteristics of a random sampling clock relative to the signal under measurement and provides design rules for synthesis of pseudo-random sampling clocks. The proposed circuit provides a way to mix a range of frequencies in a pseudo-random fashion to produce uniformly distributed edges for random sampling, which yields measurement accuracy very close to that of true random sampling. A practical circuit design technique of pseudo-random clock generation is proposed based on a standard cell approach. This allows on-chip integration of a random clock generator while keeping the overall system design-time efficient and portable across varying technologies. The proposed designs are targeted to IBM Cu-08 standard cell libraries and provide a measurement resolution of 1ps.
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