Standard cell based pseudo-random clock generator for statistical random sampling of digital signals

Abstract

Abstract-A statistical random sampling technique has recently emerged as an elegant design-time efficient technique to address many timing issues of on-chip signals. To obtain reliable measurement results, it requires uniformly distributed sampling edges within the interval defined by the periodic cycles of the signal under measurement. This paper analyzes the characteristics of a random sampling clock relative to the signal under measurement and provides design rules for synthesis of pseudo-random sampling clocks. The proposed circuit provides a way to mix a range of frequencies in a pseudo-random fashion to produce uniformly distributed edges for random sampling, which yields measurement accuracy very close to that of true random sampling. A practical circuit design technique of pseudo-random clock generation is proposed based on a standard cell approach. This allows on-chip integration of a random clock generator while keeping the overall system design-time efficient and portable across varying technologies. The proposed designs are targeted to IBM Cu-08 standard cell libraries and provide a measurement resolution of 1ps.

Design of high performance Pseudorandom Clock Generator for compressive sampling applications

“…9 (b) shows that the first transition ends at the time instance 500 and the second transition starts at the same time instance without any delay. Table 2, an analysis of the proposed PRCG performance is demonstrated and compared against the implementations published in [5] and [6]. As noticed, this work was capable to reduce the average power dissipation of the PRCG by 86.2% and 22.5% compared to the publications in [6], and [5] respectively.…”

“…PRNGs are vital in many practical aspects including PRCGs [3][4][5][6][7], Software Defined Radio (SDR) [8], Built-In Self-Test (BIST) in VLSI design [9], Evolutionary Algorithms, and Monte Carlo simulations. It is more desirable in most hardware implementations to minimize power consumption, area and maximize speed while producing high quality random numbers.…”

“…Recent advances in the past years have shown great interest in research and development of PRCGs and Random Sampling Units (RSUs). For instance, a standard cell based PRCG for statistical random sampling of digital signals has been introduced in [5]. They proposed a 5-bit circular ring slices controlled by an 8-bit Linear Feedback Shift Register (LFSR); the upper 5 bits connected to ring slices for coarse variation and the 3 lower bits connected to a delay-blender for finer variation of frequencies.…”

Data strobe timing of DDR2 using a statistical random sampling technique

“…We applied this technique in this design over high-speed on-chip signals in two manners: (1) to measure and correct the duty cycle of the system clock to produce equalized data and strobe for write cycles of source synchronous DDR/DDR2 bus, and(2) to measure and adjust the path delay of the strobe relative to the data to align the capturing edge of the strobe in the middle of the data eye. In this technique a random clock [3] is used, which is generated by a digitally controlled ring oscillator fed with pseudorandom numbers generated from a Linear Feedback Shift Register (LFSR). The capricious behavioral characteristics of a ring oscillator together with pseudo-random numbers generated by a LFSR produce a functional random clock for random observation of on-chip signals.…”

“…To measure the duty cycle of the system clock, its state is repeatedly captured and recorded at random instants of time with the help of a random clock [3]. The duty cycle is directly related to the probability of capturing a logic high (one) in a particular random observation.…”