No abstract

An analog receiver front-end chip realized in a 0.7 pm CMOS technology is presented. It uses a new, high performance, downconverter topology, called double quadrature downconverter, that achieves a phase accuracy of less than 0.3" in a large passband around 900 MHz, without requiring any external component or any tuning or trimming. A high performance low-IF receiver topology is developed with this double quadrature downconverter. The proposed low-IF receiver combines the advantages of both the classical IF receiver and the zero-IF receiver: an excellent performance and a very high degree of integration. In this way, it becomes possible to realize a true fully integrated receiver front-end that does not require a single external component and which is, different from the zero-IF receiver, nonetheless totally insensitive to parasitic baseband signals and self-mixing products.

The implementation of analog CMOS circuits that operate in the very low power supply voltage range (1 V to 2 V) becomes more important nowadays. Most accurate filter circuits are designed in the switched-capacitor technique. The existing design techniques require, however, the on-chip generation of a higher voltage by means of a voltage multiplier. In this paper, a novel technique, derived from the standard switched-capacitor technique, is presented. It is called switched-opamp because it is based on the replacement of the critical switches with opamps which are turned on and off. This technique results in a true, very low voltage operation without the need for voltage multipliers. As an example, a second order lowpass switched-capacitor filter is implemented in the switched-opamp technique. This filter operates with only a 1.5 V power supply. It is realized in a 2.4-pm CMOS process with Ti. = f 0 . 9 V. It has a measured total harmonic distortion of -60 dB for a signal swing of 600 mVPt, and a powerdrain of only 110 pW.

No abstract

No abstract