Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages

Crols, Jan; Steyaert, Michiel

doi:10.1109/4.297698

Cited by 266 publications

(79 citation statements)

References 9 publications

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“…Another completely different circuit technique that also results in an overdrive of V DD −V T is the switched opamp technique [36]. In this the SC circuit and the opamp are modified in such a way that all the switches can operate against ground or virtual ground.…”

Section: Mos Switchesmentioning

confidence: 99%

“…The opamp in the original paper [36] by Steyaert and Crols is derived from the classic Miller topology and shown in Figure 10.8. The switching is implemented with two switches, one shunting the gates of pMOS current source transistors to V DD and the other cutting off the current path between the output stage transistor M7 and V SS .…”

Section: Steyaert's Switchable Opampmentioning

confidence: 99%

“…The SO technique was first introduced in [191] and [36] and further developed in [192] by making the circuit fully differential and separating the input and output common mode levels. Reported SO circuits include filters [36,193], ∆Σ modulators [194,195], and the author's two pipelined ADCs [8,2].…”

Section: Operation Principlementioning

confidence: 99%

“…Reported SO circuits include filters [36,193], ∆Σ modulators [194,195], and the author's two pipelined ADCs [8,2].…”

Section: Operation Principlementioning

confidence: 99%

“…Typically, however, there are also series switches in the circuit input, which are not eliminated by the technique. In Steyaert's and Crols' SO circuit [36], which was a low pass biquad, two approaches were tested. The first one was a switch controlled with a voltage higher than the supply, which is, however, not a true low-voltage technique.…”

Section: Input Interfaces For So Circuitsmentioning

confidence: 99%

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Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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Section: Mos Switchesmentioning

confidence: 99%

Section: Steyaert's Switchable Opampmentioning

confidence: 99%

Section: Operation Principlementioning

confidence: 99%

“…Reported SO circuits include filters [36,193], ∆Σ modulators [194,195], and the author's two pipelined ADCs [8,2].…”

Section: Operation Principlementioning

confidence: 99%

Section: Input Interfaces For So Circuitsmentioning

confidence: 99%

See 3 more Smart Citations

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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Switched Capacitor Networks

Sánchez-Sinencio

1999

Wiley Encyclopedia of Electrical and Electronics Engineering

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Low‐voltage rail‐to‐rail switched buffer topologies

Ferri

Basçhirotto

2001

Circuit Theory & Apps

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SUMMARYThis paper presents some CMOS rail-to-rail low-voltage (1:2 V) switched bu er topologies, to be used as input stages in switched-opamp circuits. The main bu er is based on the use of an op-amp featuring rail-to-rail input and output swing with constant transconductance over the input common mode voltage. The designed bu er exhibits a total harmonic distortion of about −61dB for 5MHz clock frequency with 2 Vpp input amplitude. Its characteristics have been compared with those of other rail-to-rail switched bu ers, based on the main CMOS OTA (simple, symmetrical, Miller), showing good distortion even at frequencies in the MHz range and satisfying the requirements for the series switches.

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Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages

Cited by 266 publications

References 9 publications

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Switched Capacitor Networks

Low‐voltage rail‐to‐rail switched buffer topologies

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