Low‐voltage rail‐to‐rail switched buffer topologies

Ferri, Giuseppe; Basçhirotto, A.

doi:10.1002/cta.160

Cited by 7 publications

(6 citation statements)

References 15 publications

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“…Several low supply voltage techniques that expand the commonmode range of the gate-driven amplifiers have been proposed. The most common technique is based on parallel connected PMOS and NMOS differential pairs, but it requires complex control circuits presenting also a deadzone region in the middle of the input range [7][8][9][10][11][12]. Another technique is based on the use of dynamic level shifters and offers relatively large input common-mode range [13,14].…”

Section: Introductionmentioning

confidence: 99%

0.8 V bulk-driven operational amplifier

Raikos

Vlassis

2009

Analog Integr Circ Sig Process

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A low-voltage bulk-driven CMOS operational amplifier is proposed in this paper. The inherent small transconductance of the bulk-driven devices is enlarged using a positive feedback, improving also the noise performance. The amplifier is designed using standard 0.18 lm n-well CMOS process. Although the amplifier is optimized for 0.8 V supply voltage, it is also capable to operate under supply voltage of 0.7 V. The amplifier consumes 130 lA, performing 56 dB open-loop gain, 154 nV/HHz input-referred spot noise at 100 kHz, 80 dB CMRR at 100 kHz and IIP3 equal to -4.7 dBV.

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Section: Introductionmentioning

confidence: 99%

0.8 V bulk-driven operational amplifier

Raikos

Vlassis

2009

Analog Integr Circ Sig Process

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“…The basic component of the 1.5 bit/stage pipelined ADC consists of a Multiply-by-Two function and the accuracy and linearity performance of the Multiply-by-Two circuit will determine the precision of the whole pipelined ADC [21][22][23][24][25][26]. Figure 11(a) shows a single-ended circuit schematic and timing diagrams of Multiply-by-Two circuit which incorporates two equal capacitors C S = C F = C. The actual design adopts FD architecture to reduce the CM noise on the power and the substrate.…”

Section: The Multiply-by-two Circuit Designmentioning

confidence: 99%

“…In Section 4, two experimental circuits, i.e. a FD folded-cascode op-amp [16][17][18][19][20] with a LI-CMFB circuit and a switched-capacitor Multiply-by-Two circuit [21][22][23][24][25][26] are designed to verify the linearity performance of our proposed topology. Finally, conclusions are presented in Section 5.…”

Section: Introductionmentioning

confidence: 99%

A low distortion CMOS continuous‐time common‐mode feedback circuit

Lai

Lin

2011

Circuit Theory & Apps

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SUMMARYIn high-gain fully differential operational amplifier (FD op-amp) design, the output common-mode (CM) voltage of the FD op-amp is quite sensitive to device properties and mismatch. It is, therefore, necessary to add an additional control circuit, referred to as the common-mode feedback (CMFB) circuit, to stabilize the output CM voltage at some specified voltage. In this paper, we present a high linear CMOS continuoustime CMFB circuit based on two differential pairs and the source degeneration using MOS transistors. Theoretical analysis and SPICE simulation results are provided to validate our proposed ideas. Finally, we present two design applications of the proposed configuration, one is the FD folded-cascode op-amp and the other is the Multiply-by-Two circuit which is the key component in the popular 1.5 bit/stage pipelined analog-to-digital converter. Comparison with conventional topologies shows that the new configuration has attractive characteristics concerning their implementation in high linear analog integrated circuits.

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“…Switched-capacitor techniques have been extensively used to implement high-resolution ADCs since the matching accuracy of capacitors is inherently superior to that of resistors [12][13][14]. In conventional algorithmic ADCs, a variety of errors including comparator offsets, charge injections, and capacitor mismatches deteriorate the performance of differential non-linearity (DNL) and integral non-linearity (INL).…”

Section: Proposed Highly Linear Mdac Capacitors Based On a Double-polmentioning

confidence: 99%

A 12 b 8 kS/s 16 μW 0.35 μm CMOS algorithmic ADC for sensor interface in ubiquitous environments

Kim

Lee

2009

Analog Integr Circ Sig Process

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This work proposes a 12 b 8 kS/s ultra-lowpower CMOS algorithmic analog-to-digital converter (ADC) for sensor interface applications such as accelerometers and gyro sensors requiring high-resolution, lowpower, and small size simultaneously. The proposed ADC employs switched-bias power reduction and bias sharing circuits to minimize chip area and power dissipation. A signal-insensitive all directionally symmetric layout technique based on a double-poly CMOS process reduces capacitor mismatch in the multiplying D/A converter for 12 b-level high accuracy without additional conventional calibration schemes. Two independently generated currents with the same negative temperature coefficient are subtracted from each other to implement temperature-and supply-insensitive current and voltage references on-chip. The prototype ADC in a 0.35 lm 2P4M CMOS technology demonstrates a measured differential non-linearity and integral non-linearity within 0.15 and 0.56 LSB at 12 b and shows a maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range of 68 and 77 dB at 8 kS/s, respectively. The ADC with an active die area of 0.70 mm 2 consumes 16 lW at 8 kS/s and 2.5 V.

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Low‐voltage rail‐to‐rail switched buffer topologies

Cited by 7 publications

References 15 publications

0.8 V bulk-driven operational amplifier

0.8 V bulk-driven operational amplifier

A low distortion CMOS continuous‐time common‐mode feedback circuit

A 12 b 8 kS/s 16 μW 0.35 μm CMOS algorithmic ADC for sensor interface in ubiquitous environments

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