SUMMARYA low-voltage input stage constructed from bulk-driven PMOS transistors is proposed in this paper. It is based on a partial positive feedback and offers significant improvement of both input transconductance and noise performance compared with those achieved by the corresponding already published bulk-driven structures. The proposed input stage offers also extended input common-mode range under low supply voltage in relevant to a gate-driven differential pair. A differential amplifier based on the proposed input stage is also designed, which includes an auxiliary amplifier for the output common-mode voltage stabilization and a latch-up protection circuitry. Both input stage and amplifier circuits were implemented with 1 V supply voltage using standard 0.35 m CMOS process, and their performance evaluation gave very promising results.
This paper proposes an all digital CMOS phase interpolator suitable for high-speed multi-Gigabit serial interfaces. The topology is based on the parallel combination of identical CMOS inverters grouped in eight segments and delivers two programmable orthogonal output phases (I/Q). The phase interpolator is designed to be compliant with MIPI alliance M-PHY standard in a 65nm CMOS process. Simulation results confirm 5-bit phase resolution with less than 5% worst case phase step variation, settling time less than 2 clock cycles and power consumption about 2mW from 1.2V voltage supply.
A low-voltage bulk-driven CMOS operational amplifier is proposed in this paper. The inherent small transconductance of the bulk-driven devices is enlarged using a positive feedback, improving also the noise performance. The amplifier is designed using standard 0.18 lm n-well CMOS process. Although the amplifier is optimized for 0.8 V supply voltage, it is also capable to operate under supply voltage of 0.7 V. The amplifier consumes 130 lA, performing 56 dB open-loop gain, 154 nV/HHz input-referred spot noise at 100 kHz, 80 dB CMRR at 100 kHz and IIP3 equal to -4.7 dBV.
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