All digital phase interpolator

Tsimpos, Andreas; Souliotis, George; Demartinos, Andreas Christos; Vlassis, S.

doi:10.1109/dtis.2015.7127354

Cited by 12 publications

(46 citation statements)

References 23 publications

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“…Interpolating inverters can be implemented using gated static inverters [54], switched static inverters [55], tri-state static inverters [38,49], or current-starved inverters [37,50,56], as shown in Fig. 3.2.…”

Section: Gated Inverter Pismentioning

confidence: 99%

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A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

Lee¹

2021

Preprint

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file:///C:/Users/MWF/Downloads/Lee, Daniel Junehee.The 8-bit digital-to-time converter (DTC) to be used for a time-mode successive-approximation register analog-to-digital converter (SAR ADC) with a minimum power consumption and silicon area is presented. The architecture and the drawbacks of a conventional voltage-mode SAR ADC are discussed. The principle of time-mode circuits and benefits of their applications to mixed-signal circuits are explained. The architecture of a time-mode SAR ADC is presented. The need for an area and power-efficient DTC to be used for a time-mode SAR ADC is discussed. The principle of a DTC is explained and prior works on a DTC are reviewed. The principle of a phase interpolator (PI), to be used for a DTC, is explained and prior works on digital PIs are reviewed. The design of the proposed DTC is presented. Each block of the proposed DTC is explained using schematic and layout views. Optimal slope of the input of the PI and the condition for linear phase interpolation are investigated. Simulation results of the proposed DTC designed in TSMC 65 nm 1.0 V CMOS technology are provided. According to simulation results with BSIM4.4 device models only, the time resolution of 0.33 ps, a maximum operation frequency of 2.53 G Hz, the power consumption of 1.38 mW, and peak differential nonlinearity (DNL) and integral nonlinearity (INL) less than 0.14 least significant bit (LSB) and 0.49 LSB, respectively, for a nominal process (TT) and a temperature condition (27 C°) are achieved.

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Section: Gated Inverter Pismentioning

confidence: 99%

“…Since the number of interpolation levels using resistorbased dividers is typically small, the resolution obtained in this way is rather limited. Mismatches [54].…”

Section: Voltage Division Pismentioning

confidence: 99%

A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

Lee¹

2021

Preprint

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“…By varying α , a set of sub‐edges between x 1 and x 2 are obtained. The adjustment of α is typically achieved by gating a set of identical inverters such as gated inverters [26], switched inverters [27], tri‐state inverters [22], or current‐starved inverters [28], as shown in Figure 3. For example, for 3‐bit interpolation, a total of 16 identical gated inverters are needed, eight connected to x 1 and eight connected x 2 .…”

Section: Digital Time Interpolationmentioning

confidence: 99%

“…Otherwise, the linearity of the interpolator will deteriorate. Gated inverter shown in Figure 4a offers good input‐output isolation when the cell is not selected, or its input is grounded [26]. Switched inverter in Figure 4b suffers from poor input‐output isolation due to the existence of a direct path from the input to the output formed by the gate‐drain capacitance of the transistors [27].…”

Section: Digital Time Interpolationmentioning

confidence: 99%

An 8‐bit digital‐to‐time converter with pre‐skewing and time interpolation

Lee

Yuan

Khan

et al. 2021

IET Circuits, Devices & Systems

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This study presents an 8-bit delay line digital-to-time converter (DTC) with pre-skewing and digital time interpolation. Pre-skewing that lowers the per-stage-delay of delay lines beyond that set by the chosen technology is investigated. A cascode tri-state inverter is proposed to improve the isolation between the input and output of interpolation cells so as to improve the linearity of the time interpolator. Design considerations that critically affect the linearity of the DTC are examined in detail. The impact of the slope of the inputs of the time interpolator on the latency and linearity of the interpolator is analysed and the maximum slope of the input of interpolators yielding the minimum latency without sacrificing linearity, is obtained. The timing errors of DTC are investigated and the considerations of the layout of the DTC are examined. The DTC is designed in a TSMC 65 nm 1.0 V CMOS technology and analysed using Spectre with BSIM3V3 device models. Post-layout simulation results show the DTC offers 3.6 ps resolution, 580 MS/s conversion rate, and consumes 383 μW.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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“…A PI can potentially replace a digital-to-time converter (DTC) in many applications to generate a time delay. Several PI topologies have been proposed; Delay line based [6], [7], trigonometric [2], [8], [9], current-weighting [1], [3], [4], [10], [11], charge-steering [12] and constant-slope charging [5], [13].…”

Section: Introductionmentioning

confidence: 99%

A Low-Noise <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula>-Based Phase Interpolator in 16-nm CMOS

Jakobsson

Serban²,

Gong³

2019

IEEE Trans. Circuits Syst. II

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Abstract-This paper describes a passive analog phase interpolator, utilizing a switched RC-network. The proposed circuit eliminates the current sources in a phase interpolator based on constant-slope charging. By eliminating the current source, the noise is significantly reduced due to the reduction in thermal and flicker noise. The phase interpolator has a resolution of 6 bits and is implemented in a 16-nm CMOS process. The maximum differential non-linearity is measured to be 0.1 LSBs at a 192 ps input time delta. The circuit draws 0.2 mW from a 0.8 V supply, and occupies 0.004 mm 2 .

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All digital phase interpolator

Cited by 12 publications

References 23 publications

A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

An 8‐bit digital‐to‐time converter with pre‐skewing and time interpolation

A Low-Noise <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula>-Based Phase Interpolator in 16-nm CMOS

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