This paper proposes an all digital CMOS phase interpolator suitable for high-speed multi-Gigabit serial interfaces. The topology is based on the parallel combination of identical CMOS inverters grouped in eight segments and delivers two programmable orthogonal output phases (I/Q). The phase interpolator is designed to be compliant with MIPI alliance M-PHY standard in a 65nm CMOS process. Simulation results confirm 5-bit phase resolution with less than 5% worst case phase step variation, settling time less than 2 clock cycles and power consumption about 2mW from 1.2V voltage supply.
SUMMARYNew CMOS current di erential ampliÿers are proposed suitable for analogue signal processing at high frequencies. They consist of simple current mirrors, which are easy to design and to implement in IC form. Low-voltage low-power design is feasible. Relying on these devices a number of applications are obtained, including lossy and lossless integrators, simulated inductors, active ÿlters, and harmonic oscillators. Theoretical expressions are given for all of the proposed new circuits. The veriÿcation of the circuits is also achieved by simulation.
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