A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology

Abstract

An analog receiver front-end chip realized in a 0.7 pm CMOS technology is presented. It uses a new, high performance, downconverter topology, called double quadrature downconverter, that achieves a phase accuracy of less than 0.3" in a large passband around 900 MHz, without requiring any external component or any tuning or trimming. A high performance low-IF receiver topology is developed with this double quadrature downconverter. The proposed low-IF receiver combines the advantages of both the classical IF receiver and the zero-IF receiver: an excellent performance and a very high degree of integration. In this way, it becomes possible to realize a true fully integrated receiver front-end that does not require a single external component and which is, different from the zero-IF receiver, nonetheless totally insensitive to parasitic baseband signals and self-mixing products.

CMOS mixers and polyphase filters for large image rejection

“…These comprise a pair of SQDC mixers. It has been noted before [1], and is proven below, that image rejection depends only to the second order on quadrature inaccuracy in the LO and RF. For instance, to reject the image by 60 dB, 3% quadrature accuracy is enough for each of the RF and LO inputs, instead of the 0.1% in single-quadrature downconversion.…”

“…The double-quadrature upconversion (DQUC) topology [1] is merely the combination of the two SQUC circuits above (Fig. 17).…”

“…An interesting extension of the basic structure is the doublequadrature architecture [1]. It uses four mixers with both RF and LO inputs in quadrature phases.…”

Wireless Receiver Architectures Towards 5G: Where Are We?

“…The homodyne receiver is the most common architecture used in low-power applications due to its simplicity and scalability [10], and can be fully integrated [9], [23]. However, it suffers from DC-offset [1]- [7], [9], [10], [24]- [26], flicker noise [1], [3]- [5], [8], [10]- [12] and even-order intermodulation [1], [5], [11]- [13] issues.…”

Double modulation scheme for switching mixers controlled by sigma-delta modulators

“…Many new obstacles have to be solved to obtain a single solution IC, which leads to new front-end architectures [1], [2], [3], [4]. This paper deals with a modulation scheme, the double modulation scheme, that utilizes that clocked mixers such as the switching mixer and the subsampling mixer can be modified slightly to provide an extra modulation controlled by a 1 bit Sigma Delta modulated signal.…”