2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology

Abstract-A statistical random sampling technique has recently emerged as an elegant design-time efficient technique to address many timing issues of on-chip signals. To obtain reliable measurement results, it requires uniformly distributed sampling edges within the interval defined by the periodic cycles of the signal under measurement. This paper analyzes the characteristics of a random sampling clock relative to the signal under measurement and provides design rules for synthesis of pseudo-random sampling clocks. The proposed circuit provides a way to mix a range of frequencies in a pseudo-random fashion to produce uniformly distributed edges for random sampling, which yields measurement accuracy very close to that of true random sampling. A practical circuit design technique of pseudo-random clock generation is proposed based on a standard cell approach. This allows on-chip integration of a random clock generator while keeping the overall system design-time efficient and portable across varying technologies. The proposed designs are targeted to IBM Cu-08 standard cell libraries and provide a measurement resolution of 1ps.

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“…The concept of statistical random sampling [1][2] [3] as applied to digital VLSI signals can be understood from Fig. 1.…”

Section: Contextual Backgroundmentioning

confidence: 99%

Standard cell based pseudo-random clock generator for statistical random sampling of digital signals

Bhatti

Chugg

Draper

2007

2007 50th Midwest Symposium on Circuits and Systems

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“…A promising solution is replacing parallel bus with serial link using a SerDes transceiver [2]- [4]. Serial link based designs have been used for decades in Off-Chip Communications because it offers many advantages over traditional parallel implementations including fewer pins, reduced space requirements, reduced complexity, lower power consumption, smaller connectors, lower electromagnetic interference, and better noise immunity [5] [6]. If the number of channels is reduced where the same channel area is maintained, the significant savings in power dissipation can be achieved.…”

Section: Introductionmentioning

confidence: 99%

Design of a New Serializer and Deserializer Architecture for On-Chip SerDes Transceivers

Jaiswal¹,

Gamad²

2015

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The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes Transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues.

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Impolite High Speed Interfaces with Asynchronous Pulse Logic

Miller

Segal

Carthy

et al. 2018

Proceedings of the 2018 Great Lakes Symposium on VLSI

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We present a design solution that allows design of higher-thancore rate operation with techniques that avoid PLL/DLL blocks to provide higher speed timing. Many modern integrated circuits (ICs) have high speed interfaces which operate at higher cycle rates than the core of the IC. As a result of the higher-than-core rate, these interfaces are not directly representable in the core sequential logic. Asynchronous pulse logic offers an alternative design method for high speed interfaces with similar performance, simpler circuitry and without resorting to high-power logic cells such as emitter coupled logic. Formal and practical considerations for constructing high-speed interfaces are described. Gate designs and timing information for example cases are presented. These cases suggest that 80% improvements on rate compared traditional clocked logic are possible.

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2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology

Cited by 3 publications

References 12 publications

Standard cell based pseudo-random clock generator for statistical random sampling of digital signals

Standard cell based pseudo-random clock generator for statistical random sampling of digital signals

Design of a New Serializer and Deserializer Architecture for On-Chip SerDes Transceivers

Impolite High Speed Interfaces with Asynchronous Pulse Logic

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