A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ

Li, Xueqing; Wei, Qi; Xu, Zhiwei; Liu, Jianan; Wang, Hui; Yang, Huazhong

doi:10.1109/tcsi.2014.2332248

Cited by 31 publications

(34 citation statements)

References 28 publications

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“…Compared with [2], the settling time is relaxed from half a clock cycle to one clock cycle which highlights the advantage of relaxed-timing design. The interleaving operation also enables increased signal power and flattened spectrum envelop in the 1 st Nyquist zone [3]. Section IV will verify the effectiveness of TRI-DEMRZ.…”

Section: The Proposed Tri-demrz Techniquementioning

confidence: 94%

“…Time-relaxed interleaving digital-random-return-to-zero (TRI-DRRZ) [3] can be introduced to improve the degree of randomization for existing DEM techniques. In TRI-DRRZ, two sub DACs are alternately controlled by the thermometer decoder and random RZ signals.…”

Section: B Existing Dem and Tri-drrz Techniquesmentioning

confidence: 99%

“…For high-speed DACs, the current source mismatches [1], [2], [8]- [10], code-dependent load variations [3]- [5], [11] and code-dependent switching glitches [2]- [4], [7] are the main issues that limit the SFDR. At higher frequencies, the finite output impedance due to parasitics worsens the code-dependent load variation and deteriorates the SFDR.…”

Section: Introductionmentioning

confidence: 99%

“…The complementary switched current sources (CSCS) in [3] are employed to further compensate the code-dependent load variations due to the finite output impedance effect.…”

Section: Introductionmentioning

confidence: 99%

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A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist

Liu

Wei

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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A 14-bit 1.0-GS/s current-steering digital-to-analog converter (DAC) was designed in a 65-nm CMOS process. For such current-steering DACs with a high sampling rate, the codedependent load variations and switching glitches are a main bottleneck which limits the spurious-free dynamic range (SFDR). Dynamic element matching (DEM) has been an effective solution to randomize these glitches for a higher SFDR and also to reduce the matching requirement of the current cells for an areaefficient design which also improves the SFDR with reduced parasitic capacitance. An effective method named TRI-DEMRZ is proposed in this paper, consisting of time-relaxed interleaving, DEM and return-to-zero encoding. We also apply TRI-DEMRZ in synergy with complementary switched current sources (CSCS) to design the DAC for the purpose of a small die size and enhanced SFDR performance. Post-layout simulations show >80 dB SFDR up to the Nyquist. This DAC has a mixed 1.2 V / 2.5 V power supply and an active area of 0.48 mm 2 . Keywords-Digital-to-analog converter (DAC); mismatch; Dynamic element matching (DEM); return-to-zero (RZ); spuriousfree dynamic range (SFDR)I.978-1-4799-8391-9/15/$31.00 ©2015 IEEE

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Section: The Proposed Tri-demrz Techniquementioning

confidence: 94%

Section: B Existing Dem and Tri-drrz Techniquesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…The complementary switched current sources (CSCS) in [3] are employed to further compensate the code-dependent load variations due to the finite output impedance effect.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist

Liu

Wei

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

Self Cite

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“…Another type of interleaved DAC, which is discussed in [45,46,47], also consists of several sub-DACs in parallel, however in contrast to the work presented in this thesis and the work of [44], no multiplexer is used to combine them and instead the output currents of all sub-DACs are directly summed. While this does still double the sample rate, it does not provide the other benefits that an interleaved architecture can give.…”

Section: Interleaved Dacsmentioning

confidence: 99%

Time-interleaved high speed D/A converters

Olieman¹

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Redundancy‐bandwidth scalable techniques for signal‐independent element transition rates in high‐speed current‐steering DACs

Lai

Yang

2018

Circuit Theory & Apps

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This paper presents redundancy-bandwidth scalable techniques to deal with the intersymbol interference distortions for current-steering digital-to-analog converters in high-speed applications. A switching strategy that explores the use of redundant current sources is proposed to realize a signal-independent element transition rate, ie, the number of switching activities during the transition of successive sampling clock cycles. With a certain number of redundant current sources, this strategy significantly reduces the intersymbol interference distortions without oversampling operation or causing signal attenuation, which makes it appealing for high-speed applications. As analyzed in this paper, the number of required redundant current sources is scalable for different bandwidth requirement in specific applications, leading to 3 redundancy-bandwidth scalable trade-offs between the cost from redundant current sources and the high-dynamic-range bandwidth. In implementation, we propose a customdesigned decoder, named as the overlap-controlled data-weighted averaging (OC-DWA). Compared with the existing similar-purpose designs, the proposed OC-DWA decoder realizes the current sources selection with a simple barrel rotator, which is of much lower hardware complexity and energy consumption.Simulations of a digital-to-analog converter with this decoder exhibit an enhanced dynamic range over the entire Nyquist band, which verifies the redundancy-bandwidth scalability of the proposed techniques.

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A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ

Cited by 31 publications

References 28 publications

A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist

A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist

Time-interleaved high speed D/A converters

Redundancy‐bandwidth scalable techniques for signal‐independent element transition rates in high‐speed current‐steering DACs

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A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ

Cited by 31 publications

References 28 publications

A 14-bit 1.0-GS/s dynamic element matching DAC with &#x003E;80 dB SFDR up to the Nyquist

A 14-bit 1.0-GS/s dynamic element matching DAC with &#x003E;80 dB SFDR up to the Nyquist

Time-interleaved high speed D/A converters

Redundancy‐bandwidth scalable techniques for signal‐independent element transition rates in high‐speed current‐steering DACs

Contact Info

Product

Resources

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A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist

A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist