Redundancy‐bandwidth scalable techniques for signal‐independent element transition rates in high‐speed current‐steering DACs

Abstract

This paper presents redundancy-bandwidth scalable techniques to deal with the intersymbol interference distortions for current-steering digital-to-analog converters in high-speed applications. A switching strategy that explores the use of redundant current sources is proposed to realize a signal-independent element transition rate, ie, the number of switching activities during the transition of successive sampling clock cycles. With a certain number of redundant current sources, this strategy significantly reduces the intersymbol interference distortions without oversampling operation or causing signal attenuation, which makes it appealing for high-speed applications. As analyzed in this paper, the number of required redundant current sources is scalable for different bandwidth requirement in specific applications, leading to 3 redundancy-bandwidth scalable trade-offs between the cost from redundant current sources and the high-dynamic-range bandwidth. In implementation, we propose a customdesigned decoder, named as the overlap-controlled data-weighted averaging (OC-DWA). Compared with the existing similar-purpose designs, the proposed OC-DWA decoder realizes the current sources selection with a simple barrel rotator, which is of much lower hardware complexity and energy consumption.Simulations of a digital-to-analog converter with this decoder exhibit an enhanced dynamic range over the entire Nyquist band, which verifies the redundancy-bandwidth scalability of the proposed techniques.

Mismatch error compensation of hybrid CS‐DAC to achieve high figure of merit utilizing on‐chip self‐healing assisted swap‐enabled randomization technique

“…[1][2][3][4][5][6] Additionally, increase in resolution and frequency of operation further degrade the static and dynamic performances. [7][8][9][10] Though the effect of random mismatch can be reduced by using current cells with larger size transistors, in spite of that, this method increases the output capacitances. 2 As a result, this technique suffers from low dynamic performances at higher frequency with larger area penalty.…”

“…However, the presence of non‐ideal mismatch components in the CS‐DAC designs majorly contributes for the reduced performance and linearity 1–6 . Additionally, increase in resolution and frequency of operation further degrade the static and dynamic performances 7–10 …”

A 10‐bit 1GSample/s hybrid digital‐to‐analog converter with a modified thermometer decoder in 65‐nm CMOS technology

“…In this regard, for an N‐bit converter, M least significant bits (LSBs) are realized in binary method and the residual N‐M bits in unitary. Proper arrangement and assignment of the number of bits to binary and unitary parts are among the main design challenges and performed by a compromise between dynamic and static performance, power consumption, occupied area, and circuit complexity 10,11 …”

“…Proper arrangement and assignment of the number of bits to binary and unitary parts are among the main design challenges and performed by a compromise between dynamic and static performance, power consumption, occupied area, and circuit complexity. 10,11 To control the unit current sources in unitary and segmentation DACs, thermometer decoders are essential, which are a bottleneck for these architectures. Since the conversion delay is the major criteria of the decoder and determines the total performance of unitary and segmentation DACs, it is known that two-dimensional (2-D) structures are faster than one-dimensional (1-D) owing to parallel processing of two input code groups.…”

“…At first, the digital inputs are decoded into 1-D thermometercoded signals, and logic gates then act as the decision-maker according to the row and column locations whether the unit current source becomes on or off. 10,11 Also, in previous studies, 5,16,17 multidimensional decoders are presented, in which the input codes have been divided into more than two groups to decrease the conversion delay at the cost of a higher number of logic gates. Besides the mentioned decoder implementations, previous studies [18][19][20] introduce a new decoder design using multiplexers.…”