A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate

Jeong, Won-Ki; Im, Jae-Woo; Kim, Doo-Hyun; Nam, Sang-Wan; Shim, Dong-Kyo; Choi, Minsuk; Yoon, Hyun-Jun; Kim, Daehan; Kim, Youse; Park, Hyun-Wook; Kwak, Donghun; Park, Sang-Won; Yoon, Seok-Min; Hahn, Wook-Ghee; Ryu, Jiseon; Shim, Sang-Won; Kang, Kyung‐Tae; Ihm, Jeong-Don; Kim, In-Mo; Lee, Doo-Sub; Cho, Ji-Ho; Kim, Moo-Sung; Jang, Jae Hoon; Hwang, Sang-Won; Byeon, Dae–Seok; Yang, Hyang-Ja; Park, Kitae; Kyung, Kye-Hyun; Choi, Jung Kyu

doi:10.1109/jssc.2015.2474117

Cited by 52 publications

(10 citation statements)

References 4 publications

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“…First of all, the strong reduction of cell-to-cell electrostatic interference allowed to simplify and speed up the programming schemes adopted by TLC technologies. In this regard, direct single-round programming of the memory cells to the 8 V T states needed for TLC storage replaced more complex and time-consuming multiple-round programming schemes [23], [68]. Then, the reduction of cell-to-cell electrostatic interference along with the reduction of program noise, RTN, and charge detrapping allowed to achieve and keep narrower cell V T distributions.…”

Section: B Outcomes Of the Reliability Improvements Allowed By The 3-d Transitionmentioning

confidence: 99%

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Compagnoni

Spinelli

2019

IEEE Trans. Electron Devices

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This paper reviews what changed in the reliability of NAND Flash memory arrays after the paradigm shift in technology evolution determined by the transition from 2-D to 3-D integration schemes. Starting from a quick glance at the fundamentals of raw array reliability, the reasons for its worsening with the evolution of 2-D technologies will be discussed, focusing on the physical phenomena which contributed more to that outcome. By exploring the dependence of the magnitude of these phenomena on cell and array parameters, the abrupt improvements achieved from the 3-D transition in terms of raw array reliability will then be explained, highlighting also that these improvements were turned into new opportunities for the technology. Finally, the physical issues specific to 3-D arrays will be addressed, providing a glimpse of the challenges that the NAND Flash technology will have to face from the standpoint of array reliability in the near future. Index Terms-3-D NAND Flash arrays, Flash memories, semiconductor device modeling, semiconductor device reliability. I. INTRODUCTIONT HE NAND Flash technology has become, today, the undisputed leader in the nonvolatile memory market, largely overcoming the hard-disk drive (HDD) technology in terms of revenues [1]. This outcome has been determined by the capability of the NAND Flash solution to address quite a variety of applications better than any other storage technology, thanks to successful tradeoffs among cost, performance, and reliability. At the heart of all that there is, of course, the possibility to steadily increase the integration density of the NAND array and, in turn, the memory capacity per chip. This is clearly proved in Fig. 1 in terms of gross bit storage density (GBSD), i.e., the ratio between the storage capacity and the total chip area, of the NAND Flash chips presented at the IEEE International Solid-State Circuits Conference (IEEE ISSCC) since 2001 (see [2] for further details on the analysis methodology).Up to ∼2015, the GBSD increase was achieved, first of all, through a constant pace miniaturization of the memory cells

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Section: B Outcomes Of the Reliability Improvements Allowed By The 3-d Transitionmentioning

confidence: 99%

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Compagnoni

Spinelli

2019

IEEE Trans. Electron Devices

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“…Among these, WL and BL delays are limiting factors, especially for devices with large memory arrays, such as NAND flash and storage class memories. Pre-emphasis (PE) pulses are design techniques to reduce the access line delay of 3D NAND devices [1] and large flat panel displays [2]. By driving large RC delay lines with a pulse whose initial period is made with a voltage higher than the target voltage, the entire WL delay time can be reduced significantly, where the delay time is defined by the farthest point of WL.…”

Section: Introductionmentioning

confidence: 99%

Pre-Emphasis Pulse Design for Reducing Bit-Line Access Time in NAND Flash Memory

Kondo

Tanzawa

2022

Electronics

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This paper describes pre-emphasis (PE) pulses to reduce bit-line (BL) access time in NAND flash memory. Optimum PE pulse widths and resultant minimum BL delay times are investigated, where the BL delay is determined by the sense current at the input terminal of a sensing circuit in contrast with the word-line (WL) delay that is determined by the WL voltage at the gate of a selected memory cell. Two BL models are used, namely, a single-line model (SLM) for the shielded BL read operation and a three-line model (TLM) for the all-BL read operation. Under the condition that the sense current delay is defined by the time when the sense current becomes stable between 110% and 90% of the cell current and the BL voltage delay is defined by the time when the BL voltage at the selected cell reaches a window between 110% and 90%, SPICE simulation results show that the sensed current delay and the BL voltage delay are reduced by 43% and 36% in the case of SLM and by 16% and 28% in the case of TLM, respectively. Thus, the key results are the following: (1) PE pulses are effective to reduce the sense current delay time for BL access, as well as the BL voltage delay time for both SLM and TLM; (2) the sensitivity of the PE pulse on the delay time is much larger for the sensed current delay than the BL voltage delay due to the absence of filtering with the RC delay element in BL delay; and (3) address-dependent PE pulse control can reduce the sense current delay significantly, especially for access to cells closely located to the sensing circuit.

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“…Since the release of the 3D NAND flash product for the first time in 2014 [1], the bit density could be increased rapidly by increasing the number of WL (Word line) stacking layers, which starts at 24, came up to 128 [1][2][3][4][5][6], and it is unpredictable how many it will increase to fulfill the explosive growth of data demand. In this situation, while increasing the number of stacked WL layers, the mold stacking height should be scaled down due to the limitations of the channel hole etching process.…”

Section: Introductionmentioning

confidence: 99%

A New Read Scheme for Alleviating Cell-to-Cell Interference in Scaled-Down 3D NAND Flash Memory

2020

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In this paper, we investigated the cell-to-cell interference in scaled-down 3D NAND flash memory by using a Technology Computer-Aided Design (TCAD) simulation. The fundamental cause of cell-to-cell interference is that the electric field crowding point is changed by the programmed adjacent cell so that the electric field is not sufficiently directed to the channel surface. Therefore, the channel concentration of the selected cell is changed, leading to a Vth shift. Furthermore, this phenomenon occurs more severely when the selected cell is in an erased state rather than in a programmed state. In addition, it was confirmed that the cell-to-cell interference by the programmed WLn+1 is more severe than that of WLn−1 due to the degradation of the effective mobility effect. To solve this fundamental problem, a new read scheme is proposed. Through TCAD simulation, the cell-to-cell interference was alleviated with a bias having a ΔV of 1.5 V from Vread through an optimization process to have appropriate bias conditions in three ways that are suitable for each pattern. As a result, this scheme narrowed the Vth shift of 67.5% for erased cells and narrowed the Vth shift of 70% for programmed cells. The proposed scheme is one way to solve the cell-to-cell interference that may occur as the cell-to-cell distance decreases for a high stacked 3D NAND structure.

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A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate

Cited by 52 publications

References 4 publications

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Pre-Emphasis Pulse Design for Reducing Bit-Line Access Time in NAND Flash Memory

A New Read Scheme for Alleviating Cell-to-Cell Interference in Scaled-Down 3D NAND Flash Memory

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