A New Read Scheme for Alleviating Cell-to-Cell Interference in Scaled-Down 3D NAND Flash Memory

Abstract

In this paper, we investigated the cell-to-cell interference in scaled-down 3D NAND flash memory by using a Technology Computer-Aided Design (TCAD) simulation. The fundamental cause of cell-to-cell interference is that the electric field crowding point is changed by the programmed adjacent cell so that the electric field is not sufficiently directed to the channel surface. Therefore, the channel concentration of the selected cell is changed, leading to a Vth shift. Furthermore, this phenomenon occurs more severely when the selected cell is in an erased state rather than in a programmed state. In addition, it was confirmed that the cell-to-cell interference by the programmed WLn+1 is more severe than that of WLn−1 due to the degradation of the effective mobility effect. To solve this fundamental problem, a new read scheme is proposed. Through TCAD simulation, the cell-to-cell interference was alleviated with a bias having a ΔV of 1.5 V from Vread through an optimization process to have appropriate bias conditions in three ways that are suitable for each pattern. As a result, this scheme narrowed the Vth shift of 67.5% for erased cells and narrowed the Vth shift of 70% for programmed cells. The proposed scheme is one way to solve the cell-to-cell interference that may occur as the cell-to-cell distance decreases for a high stacked 3D NAND structure.

Optimizing Confined Nitride Trap Layers for Improved Z-Interference in 3D NAND Flash Memory

“…Figure 1a,b show transmission electron microscopy (TEM) images of cross-sections of a 3D NAND with a confined nitride trapping layer [13]. Figure 1c,d show schematic cross-sections of the 3D NAND with the confined nitride trapping layer used in the TCAD simulation.…”

“…Various research endeavors have been pursued to address this issue, primarily focusing on enhancing operational conditions. Initially, a method proposing the application of a high read voltage to the adjacent WL during read operations was introduced [12,13]. However, this approach poses the risk of exacerbating read disturbance across the entire block due to the elevated read bias of the adjacent WL.…”

A Review of Cell Operation Algorithm for 3D NAND Flash Memory

“…This method increases the read time overhead and the additional latch that stores the WLn + 1 pre-sensing result must be inserted [32]. J.-M. Sim et al demonstrated that when reading the WLn, cell-to-cell interference can be greatly improved by adding an offset read bias of 1.5 V or more to adjacent WLs compared to unselected WL [76]. In general, cell-to-cell interference is worsen when the channel potential of WLn changes rapidly right after WLn + 1 is programmed.…”

Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors

“…From the perspective of channel potential, the NWI can be investigated more intuitively and accurately. In this way, some studies reduced NWI by enhancing the applied to neighbor cells [ 24 ] or by adopting reverse order program [ 25 ].…”