A Review of Cell Operation Algorithm for 3D NAND Flash Memory

Park, Jong Kyung; Kim, Sarah Eunkyung

doi:10.3390/app122110697

Cited by 5 publications

(1 citation statement)

References 87 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Recently, in-memory computing has attracted great interest, due to its ability to effectively improve the processing efficiency of big data. As a strong device candidate for in-memory computing, silicon-based 3D NAND flash memory with perfect compatibility with CMOS technology has attracted much attention [ 1 , 2 , 3 , 4 , 5 ]. However, the traditional 3D NAND flash, based on a polysilicon floating gate, is confronted with the current leakage problem, which is induced by random defects in the tunnel oxide layer after repeated erasing and writing [ 6 , 7 , 8 ].…”

Section: Introductionmentioning

confidence: 99%

Controlling the Carrier Injection Efficiency in 3D Nanocrystalline Silicon Floating Gate Memory by Novel Design of Control Layer

et al. 2023

Nanomaterials

View full text Add to dashboard Cite

Three-dimensional NAND flash memory with high carrier injection efficiency has been of great interest to computing in memory for its stronger capability to deal with big data than that of conventional von Neumann architecture. Here, we first report the carrier injection efficiency of 3D NAND flash memory based on a nanocrystalline silicon floating gate, which can be controlled by a novel design of the control layer. The carrier injection efficiency in nanocrystalline Si can be monitored by the capacitance–voltage (C–V) hysteresis direction of an nc-Si floating-gate MOS structure. When the control layer thickness of the nanocrystalline silicon floating gate is 25 nm, the C–V hysteresis always maintains the counterclockwise direction under different step sizes of scanning bias. In contrast, the direction of the C–V hysteresis can be changed from counterclockwise to clockwise when the thickness of the control barrier is reduced to 22 nm. The clockwise direction of the C–V curve is due to the carrier injection from the top electrode into the defect state of the SiNx control layer. Our discovery illustrates that the thicker SiNx control layer can block the transfer of carriers from the top electrode to the SiNx, thereby improving the carrier injection efficiency from the Si substrate to the nc-Si layer. The relationship between the carrier injection and the C–V hysteresis direction is further revealed by using the energy band model, thus explaining the transition mechanism of the C–V hysteresis direction. Our report is conducive to optimizing the performance of 3D NAND flash memory based on an nc-Si floating gate, which will be better used in the field of in-memory computing.

show abstract