A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS

Chang, Kwuang-Han; Hsieh, Chih-Cheng

doi:10.1109/asscc.2016.7844159

Cited by 16 publications

(6 citation statements)

References 3 publications

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“…The proposed SAR ADC reached the level of the research front. The FoM of the proposed SAR ADC at Nyquist was low among ADCs [34][35][36][37][38][39]. The proposed calibration method was helpful for improving static and dynamic performance.…”

Section: Measurement Resultsmentioning

confidence: 96%

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A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

Zheng

Ren

2022

Electronics

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This paper presents a 12-bit, 100 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on a bridge capacitor array with redundancy and non-linearity calibration. The differential non-linearity calibration method was proposed to compensate for the linearity, which is degraded by the parasitic capacitance of the bridge capacitor. To reduce the power dissipation and alleviate the settling error of the DAC capacitor array, a hybrid redundant scheme was proposed. A low-power, high-performance SAR ADC was implemented based on the proposed techniques. This SAR ADC prototype was implemented in 28 nm CMOS technology. Measurement results showed that the proposed SAR ADC could achieve a (signal-to-noise distortion ratio) SNDR of 61.46 dB and 58.82 dB at low and Nyquist input frequencies, respectively, resulting in figure of merits (FOMs) of 8.69 fJ/conversion and 11.8 fJ/conversion step, respectively. The SAR ADC core occupied an active area 0.0227 mm2.

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Section: Measurement Resultsmentioning

confidence: 96%

“…Table 2 compares the proposed SAR ADC with other high-performance SAR ADCs [34][35][36][37][38][39]. The proposed SAR ADC reached the level of the research front.…”

Section: Measurement Resultsmentioning

confidence: 97%

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

Zheng

Ren

2022

Electronics

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“…Table .3 summaries the performance and compares our work with recent arts, the proposed SAR ADC has reached the level of the research front. Besides, the FoM of the proposed SAR ADC at Nyquist is lowest among ADCs [11], [20], [24], [25], [26].…”

Section: Figure 26 Chip Photograph and Layout Zoomed-in View Of Sar Adcmentioning

confidence: 99%

A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET

Zheng

Lan

et al. 2021

IEEE Access

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This paper presents an energy-saving and high-resolution successive approximation register (SAR) analog-to-digital converter (ADC) with 14-nm CMOS FinFET technology for wireless communication system. An Equivalent Split-Capacitor is proposed to enlarge redundancy range and alleviate the settling error of the bridge capacitor array. A hybrid capacitor switching procedure is adopted to reduce power consumption and the variation of input common-mode voltage of the comparator. Measurement results of the 14-nm CMOS SAR-ADC achieves a SNDR of 61.29 dB and 58.34dB at low and Nyquist input frequency, respectively, resulting in figure-of-merits(FoMs) of 8.2 and 11.15fJ/conversion-step, respectively. The ADC core occupies an active area 0.112mm 2 .INDEX TERMS SAR ADC, 14-nm CMOS FinFET, Equivalent Split-Capacitor, hybrid capacitor switching procedure, figure-of-merits(FoMs).

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“…In the past days, the conversion rate of SAR ADC is limited and the pipelined ADC [1][2][3][4][5] is the mainstream architecture. With the scaling down of the transistor size, the single-channel SAR ADCs [6][7][8][9][10] can achieve hundreds of MS/s sampling rate with resolution no less than 10bit. Meanwhile, the hybrid structure pipelined SARs [11][12][13] are popular to realize the high-speed mediumresolution ADC.…”

Section: Introductionmentioning

confidence: 99%

A high-speed low-power SAR ADC in 40nm CMOS with combined energy-efficient techniques

Huang

Meng

et al. 2021

IEICE Electron. Express

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In this paper, a high-speed low-power SAR ADC is designed. In this prototype, an improved switching scheme combined with the optimized attenuation capacitor architecture is proposed, showing more power efficiency and is more suitable for high-speed data converters. Meanwhile, an improved synchronous timing strategy is employed, achieving flexible time allocation of DAC settling and comparison in each bit-cycle. In addition, a two-stage non-tail-current-source and single-phaseclock comparator is proposed with more power-efficiency and compatible resolving time. The prototype ADC is fabricated in a 40nm CMOS technology and occupies an active area of 0.04mm 2 . An SNDR of 57.18dB and an SFDR of 75.29dB are achieved with the Nyquist rate input at a sampling rate of 160MS/s, consuming 1.3mW at 1.1V supply voltage.

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A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS

Cited by 16 publications

References 3 publications

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET

A high-speed low-power SAR ADC in 40nm CMOS with combined energy-efficient techniques

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