A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET

Abstract

This paper presents an energy-saving and high-resolution successive approximation register (SAR) analog-to-digital converter (ADC) with 14-nm CMOS FinFET technology for wireless communication system. An Equivalent Split-Capacitor is proposed to enlarge redundancy range and alleviate the settling error of the bridge capacitor array. A hybrid capacitor switching procedure is adopted to reduce power consumption and the variation of input common-mode voltage of the comparator. Measurement results of the 14-nm CMOS SAR-ADC achieves a SNDR of 61.29 dB and 58.34dB at low and Nyquist input frequency, respectively, resulting in figure-of-merits(FoMs) of 8.2 and 11.15fJ/conversion-step, respectively. The ADC core occupies an active area 0.112mm 2 .INDEX TERMS SAR ADC, 14-nm CMOS FinFET, Equivalent Split-Capacitor, hybrid capacitor switching procedure, figure-of-merits(FoMs).

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

“…The proposed SAR ADC reached the level of the research front. The FoM of the proposed SAR ADC at Nyquist was low among ADCs [34][35][36][37][38][39].…”

“…The proposed SAR ADC reached the level of the research front. The FoM of the proposed SAR ADC at Nyquist was low among ADCs [34][35][36][37][38][39]. The proposed calibration method was helpful for improving static and dynamic performance.…”

“…Table 2 compares the proposed SAR ADC with other high-performance SAR ADCs [34][35][36][37][38][39]. The proposed SAR ADC reached the level of the research front.…”

A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue Amplifiers

“…With the advent of a pipelined SAR ADC architecture [6], using a dynamic amplifier (DA) as a residue amplifier has been attracting considerable attentions [7][8][9][10][11][12][13][14][15][16][17][18][19][20]. Since the DA does not draw static current, this approach can lead to a fully dynamic and hence very power-efficient implementation given that the successiveapproximation register (SAR) ADC [21][22][23] in the stage typically does not consume static power.…”