A novel automatic bridge linking capacitance and resistance has been developed. This bridge with only one 10 nF capacitance and one 10 kΩ resistance standard, operating at 1592 Hz, is implemented based on digital compensation techniques. The standards are all defined as four terminal-pair impedances. All voltages applied to the bridge are generated by a multiphase direct-digital-synthesis sine wave source, a special channel of which provided accurate phase and constant amplitude when the phase is changed. In contrast with the conventional quadrature bridge, a lot of inductive dividers and a series of balancing processes are avoided. Preliminary experimental results indicate a relative uncertainty of four parts in 107 is obtained and could be improved further.
This paper presents an energy-saving and high-resolution successive approximation register (SAR) analog-to-digital converter (ADC) with 14-nm CMOS FinFET technology for wireless communication system. An Equivalent Split-Capacitor is proposed to enlarge redundancy range and alleviate the settling error of the bridge capacitor array. A hybrid capacitor switching procedure is adopted to reduce power consumption and the variation of input common-mode voltage of the comparator. Measurement results of the 14-nm CMOS SAR-ADC achieves a SNDR of 61.29 dB and 58.34dB at low and Nyquist input frequency, respectively, resulting in figure-of-merits(FoMs) of 8.2 and 11.15fJ/conversion-step, respectively. The ADC core occupies an active area 0.112mm 2 .INDEX TERMS SAR ADC, 14-nm CMOS FinFET, Equivalent Split-Capacitor, hybrid capacitor switching procedure, figure-of-merits(FoMs).
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