2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2020
DOI: 10.1109/apccas50809.2020.9301652
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A 16-channel 50MS/s 14bit Pipelined-SAR ADC for Integrated Ultrasound Imaging Systems

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Cited by 6 publications
(2 citation statements)
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“…The power consumption is 101.5 µW from a 1 V power supply. To achieve the best power and area efficiency, Wu et al [65] presented a 16-channel 14-bit pipelined-SAR ADC for integrated UIS implemented in a 0.18μm process (as shown in Figure 17a). The ADC, designed with complete peripheral circuits including low voltage differential signaling (LVDS), serial peripheral interface (SPI), bandgap, etc., occupies an area of 0.625 mm 2 and achieves a peak SFDR of 85.6 dB, a SNDR of 66.8 dB at 50 MS/s sampling rate.…”
Section: Hybrid Adcmentioning
confidence: 99%
“…The power consumption is 101.5 µW from a 1 V power supply. To achieve the best power and area efficiency, Wu et al [65] presented a 16-channel 14-bit pipelined-SAR ADC for integrated UIS implemented in a 0.18μm process (as shown in Figure 17a). The ADC, designed with complete peripheral circuits including low voltage differential signaling (LVDS), serial peripheral interface (SPI), bandgap, etc., occupies an area of 0.625 mm 2 and achieves a peak SFDR of 85.6 dB, a SNDR of 66.8 dB at 50 MS/s sampling rate.…”
Section: Hybrid Adcmentioning
confidence: 99%
“…For a three-stage architecture in (b), the sharing scheme maximizes the efficiency with one op-amp and only two references are shared between stages. A detailed comparison of area and power consumption[29,30] of these pipelined-SAR ADCs is made in the following sections.…”
mentioning
confidence: 99%