A high-speed low-power SAR ADC in 40nm CMOS with combined energy-efficient techniques

Huang, Yujia; Meng, Qiao; Li, Fēi; Wu, Jie

doi:10.1587/elex.18.20210156

Cited by 5 publications

(6 citation statements)

References 30 publications

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“…Furthermore, the CDAC reference voltage switching schemes can decrease the power supply voltage and increase the speed of the conversion process . Moreover, the diferent algorithm schemes can diminish the number of iterations for the conversion process [90][91][92][93][94][95][96][97][98][99][100]. In addition, the SAR ADC architecture is suitable for fne CMOS processes [101].…”

Section: Sar Adc Architecturementioning

confidence: 99%

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Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.

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Section: Sar Adc Architecturementioning

confidence: 99%

“…Tus, the conversion clock is faster (N + 1) times that of the sampling Synchronous clock. A modifed synchronous timing strategy [90] is used for a fxed time in each cycle and variable time in DAC and comparator timing. Te settling time of DAC is stretched, and the comparison time is diminished.…”

Section: Sar Register and Its Control Logicmentioning

confidence: 99%

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

View full text Add to dashboard Cite

show abstract

“…It is worth noting that the majority of the overall power consumption is attributed to the digital-to-analog converter (DAC), which is specifically allocated for the capacitor array as well as switching mechanism [38,39]. One of the primary concerns in mitigating energy consumption involves the shrinking of array capacitors along with the implementation of alternative approaches [6]. This paper presents energy efficient switching scheme based capacitive digital to analog converter (CDAC) in figure 5.…”

Section: Dacmentioning

confidence: 99%

“…So there exists a tradeoff between power consumption in an ADC circuit and its maximum operating frequency [5]. Power consumption increases substantially with an increase in the operating speed of a device [6]. In a SAR ADC, comparator and digital to analog converter (DAC) modules are the major contributors of power consumption in the circuit implementation.…”

Section: Introductionmentioning

confidence: 99%

Design of 8 -bit low power SAR ADC in 45 nm for biomedical implants

Tyagi,

Mittal,

Kumar

2023

Phys. Scr.

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The utilisation of low power SAR (Successive Approximation Register) Analog-to-Digital Converters holds significant importance in the domain of bio-medical signal acquisition. The present study showcases the utilisation of an 8-bit CMOS SAR-ADC for integration into the analog front end of bio-signal acquisition. The focus of this technology pertains to the monitoring of implanted bio-signal devices, with a specific emphasis on ECG/EEG signals. A capacitive digital-to-analog converter (DAC) is suggested as a means to attain power consumption in the microwatt range. This approach enables comparisons to be made without any energy consumption, leading to a substantial enhancement in energy efficiency. Furthermore, a comprehensive theoretical examination of comparator offset voltages has been conducted to enhance the offset performance of the comparator operating at low supply voltage. The analysis indicates that optimization of the comparator is achieved solely through the adjustment of transistor sizes, without the implementation of any specific offset cancellation techniques. Simulations indicate that the optimization of the offset voltage to approximately 5 mV occurs when there is variation in the common-mode input voltage at a 1 V supply. The proposed Analog-to-Digital Converter (ADC) layout has been successfully executed utilizing the 45 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The Analog-to-Digital Converter (ADC) attains a Spurious-Free Dynamic Range (SFDR) of 64.02 dB and consumes 1.9 μW of power at a sampling rate of 1.1 MHz and a supply voltage of 1 V.

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“…Introduction: A wide range of mobile computing devices and health care applications currently require the use of successive approximation analog-to-digital converters (SAR ADC) [1]. Comparator is the primary component of SAR ADC, which play a crucial function by being able to transform tiny analog signal voltages into digital signals.…”

mentioning

confidence: 99%

A 1.2 V high‐speed low‐power preamplifier latch‐based comparator

Guo-shun

2022

Electronics Letters

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The power consumption of chips has emerged as a major concern with the increased integration of analog circuitry. This work focuses on a two‐stage comparator based on a preamplifier with latch for a successive approximation analog‐to‐digital converter. In order to minimize power loss and delay time, the charge steering approach was used in the design of latch as well as preamplifier. The suggested comparator is simulated in SMIC 0.18‐um process in comparison to the comparator without charge steering mode. The results reveal that the average power consumption is only around 22 uW for varied input voltage at a supply voltage of 1.2 V, which is relatively lowered by approximately 30%. Meanwhile, delay time is also reduced by about 25%.

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A high-speed low-power SAR ADC in 40nm CMOS with combined energy-efficient techniques

Cited by 5 publications

References 30 publications

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Design of 8 -bit low power SAR ADC in 45 nm for biomedical implants

A 1.2 V high‐speed low‐power preamplifier latch‐based comparator

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