In this paper, we propose an optimized method for nonlinear function approximation based on multiplierless piecewise linear approximation computation (ML-PLAC), which we call OML-PLAC. OML-PLAC finds the minimum number of segments with the predefined fractional bit width of input/output, maximum number of shift-and-add operations, user-defined widths of intermediate data, and maximum absolute error (MAE). In addition, OML-PLAC minimizes the actual MAE as much as possible by iterating. As a result, under the condition of satisfying the maximum number of segments, the MAE can be minimized. Tree-cascaded 2-input and 3-input multiplexers are used to replace multi-input multiplexers in hardware architecture as well, reducing the depth of the critical path. The optimized method is applied to logarithmic, antilogarithmic, hyperbolic tangent, sigmoid and softsign functions. The results of the implementation prove that OML-PLAC has better performance than the current state-of-the-art method.
The physical unclonable function based on ring oscillator(RO PUF) is a traditional design suitable for FPGA implementation, but such designs have the disadvantage of low hardware efficiency. This article proposes a new FPGA-based ring oscillator PUF, called loop delay configurable(LDC) PUF. The construction of LDC PUF relies on configurable delay units(CDUs). An LDC PUF configured with 𝑛 CDUs can generate 2 𝑛−1 (2 𝑛 − 1) response bits. Additionally, we apply the programmable delay lines technology to enhance the reliability of LDC PUF. Compared with the traditional RO PUFs, the LDC PUF has good uniqueness(48.52%) and reliability(96.91%), and most importantly, it has ultra-low hardware cost.
A new low-voltage CMOS bandgap reference (BGR) that achieves high temperature stability is proposed. It feeds back the output voltage to the curvature compensation circuit that constitutes a closed loop circuit to cancel the logarithmic term of voltage V BE . Meanwhile a low voltage amplifier with the 0.5 µm low threshold technology is designed for the BGR. A high temperature stability BGR circuit is fabricated in the CSMC 0.5 µm CMOS technology. The measured result shows that the BGR can operate down to 1 V, while the temperature coefficient and line regulation are only 9 ppm/ • C and 1.2 mV/V, respectively.
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