A 103-dB SFDR Calibration-Free Oversampled SAR ADC With Mismatch Error Shaping and Pre-Comparison Techniques

Shen, Yuting; Li, Hanyue; Xin, Haoming; Cantatore, Eugenio; Harpe, Pieter

doi:10.1109/jssc.2021.3135559

Cited by 18 publications

(18 citation statements)

References 23 publications

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“…By using a VCM-based hybrid switching and an MSB sampling-segmented capacitor array, Z Li et al are able to achieve a low power consumption of 16.5 μW at 180 nm [49]. Y Shen uses a flying-capacitor sampling technique to achieve an astounding power consumption of 0.656 μW for a 14-bit prototype at 65 nm [50]. Z Du's OSAS scheme at 180 nm for 16 bits uses tailored shuffling to attain a noteworthy SNR of 30.2 dB [51].…”

Section: Performance Evaluation Of Sar-adcmentioning

confidence: 99%

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Singh,

Tripathi,

Mahmud

2024

Eng. Res. Express

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This study gives a thorough analysis of the performance of a 45 nm CMOS process-designed 16-bit 500 MS/s successive approximation register analog-to-digital converter (SAR-ADC). 16-bit R-2R DAC double-tail dynamic latch, Widlar current method, variable body-biasing technique, sample and hold block, 16-bit SAR, and 16-bit latch are used to design proposed SAR-ADC block. The SAR-ADC design and simulations were carried out using Cadence Virtuoso software. This powerful electronic design automation (EDA) tool facilitated the design, layout, and simulation of the ADC, ensuring a comprehensive analysis of its performance characteristics. MATLAB was used for post-simulation data analysis, processing, and visualization. The proposed SAR-ADC is compared with few existing examples listed as ADS8881, LTC2380-16, ADS8344, LTC2368, and MAX11156 on the performance metrics including signal-to-noise ratio (SNR), figure of merit (FOM), total harmonic distortion (THD), resolution, delay, power consumption and Figure of Merit (FOM). This work is highlighting different aspects of the suggested architecture and demonstrates how it outperforms benchmark of ADCs in terms of power usage, SNR, THD, and FOM. A SAR-ADC attains a power consumption of 39.2 µW while operating at sampling frequency of 500 MS/s at supply voltage of 1V. The results provide fresh perspectives for potential improvements in existing work in terms of reduction in power consumption and high-speed ADC at 16-bit resolution and also Jitter is scrutinized across various stages of the SAR-ADC. The proposed low power, high speed and high-resolution SAR ADC is targeted for high-quality analog-to-digital signal conversion useful in industrial automation systems, medical devices, IoT and audio processing modules.

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Section: Performance Evaluation Of Sar-adcmentioning

confidence: 99%

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Singh,

Tripathi,

Mahmud

2024

Eng. Res. Express

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“…The idea for designing the comparator is to compare the MSB of the input signal and threshold value [12]. If A 3 is greater than Thr 3 , then "1" will be displayed in the output.…”

Section: Design Of 3-bit Magnitude Comparatormentioning

confidence: 99%

An Improved Design of Absolute-value Detector by Using Optimized Ripple Adder

Yang

2023

J. Phys.: Conf. Ser.

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Absolute-value detector (AVD) is one of the most basic bit-operating devices, which compares the magnitude of two inputs. However, the traditional 4-bit AVD is not only time-consuming but also has a high energy consumption. This paper uses a hybrid design to optimize the 4-bit AVD by introducing an improved ripple adder in the absolute value extraction part, which then can be less energy-consuming and requires fewer transistors. The paper divides the design of AVD into an absolute value extraction part and a comparator. The input (2’s complement) can be positive or negative numbers in the absolute value extraction part. By observing the most significant bit (MSB) of the input, the design can determine the sign of input and output magnitude. For the comparator, this paper uses a logic of step-by-step comparison from the most to the least significant bits. Then, this paper finds the minimum delay of the design by critical path analysis and gate sizing. The final delay is set at 1.5 times its minimum. Device voltage optimization is applied for calculating the energy consumption. Finally, with 1.5 times the minimum delay, the energy consumption is 40% less than the consumption when the delay is the minimum.

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“…The main drawback of MES is that the presetting of the CDAC also feeds back the previous input signal, which occupies a part of the input range. This issue can be mitigated by using larger bits of MSB [133] , digital prediction [135] , or pre-comparison [136] .…”

Section: Dac Mismatchmentioning

confidence: 99%

Trending IC design directions in 2022

Chan¹,

Cheng²,

Deng³

et al. 2022

J. Semicond.

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For the non-stop demands for a better and smarter society, the number of electronic devices keeps increasing exponentially; and the computation power, communication data rate, smart sensing capability and intelligence are always not enough. Hardware supports software, while the integrated circuit (IC) is the core of hardware. In this long review paper, we summarize and discuss recent trending IC design directions and challenges, and try to give the readers big/cool pictures on each selected small/hot topics. We divide the trends into the following six categories, namely, 1) machine learning and artificial intelligence (AI) chips, 2) communication ICs, 3) data converters, 4) power converters, 5) imagers and range sensors, 6) emerging directions. Hope you find this paper useful for your future research and works.

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A 103-dB SFDR Calibration-Free Oversampled SAR ADC With Mismatch Error Shaping and Pre-Comparison Techniques

Cited by 18 publications

References 23 publications

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

An Improved Design of Absolute-value Detector by Using Optimized Ripple Adder

Trending IC design directions in 2022

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A 103-dB SFDR Calibration-Free Oversampled SAR ADC With Mismatch Error Shaping and Pre-Comparison Techniques

Cited by 18 publications

References 23 publications

Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications

Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications

An Improved Design of Absolute-value Detector by Using Optimized Ripple Adder

Trending IC design directions in 2022

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Product

Resources

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Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications