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This paper presents a reconfigurable, low offset, low noise and high speed dynamic clocked-comparator for medium to high resolution Analog to Digital Converters (ADCs). The proposed comparator reduces the input referred noise by half and shows a better output driving capability when compared with the previous work. The offset, noise and power consumption can be controlled by a clock delay which allows simple reconfiguration. Moreover, the proposed offset calibration technique improves the offset voltage from 11.6mV to 533µV at 1 sigma. A prototype of the comparator is implemented in 90nm 1P8M CMOS with experimental results showing 320µV input referred noise at 1.5GHz with 1.2V supply.

This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and V cm -based switching. The static linearity performance, namely the integral nonlinearity and differential nonlinearity, as well as the parasitic effects of the split DAC, are analyzed hereunder. In addition, a code-randomized calibration technique is proposed to correct the conversion nonlinearity in the conventional SAR ADC, which is verified by behavioral simulations, as well as measured results. Performances of both switching methods are demonstrated in 90 nm CMOS. Measurement results of power, speed, and linearity clearly show the benefits of using V cm -based switching.

An 8b 1GS/s ADC is presented that interleaves two 2b/cycle SARs. To enhance speed and save power, the prototype utilizes segmentation switching and custom-designed DAC array with high density in a low parasitic layout structure. It operates at 1GS/s from 1V supply without interleaving calibration and consumes 3.8mW of power, exhibiting a FoM of 24fJ/conversion step. The ADC occupies an active area of 0.013mm 2 in 65nm CMOS including on-chip offset calibration.

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The successive-approximation (SA) algorithm is traditionally used for lowbandwidth applications because it requires n clock cycles or more to obtain nbit resolution. However, the use of modern nanometer CMOS technologies and special design solutions overcome the speed limit, enabling conversion rates in the hundreds of MHz with very low power consumptions [1]. This design uses the successive-approximation method to obtain 8b up to 400MS/s with very low power using a 1.2V supply. Key features of the architecture are a resistive DAC and a 2b-per-cycle conversion with interpolated sampling front-ends and shift registers. A cross-coupled bootstrapping network is also implemented to alleviate the signal-dependent clock feed-through. The very compact layout leads to a silicon area of 0.024 mm 2 .Converting more than one bit per cycle in SA schemes requires using multiple reference voltages that scale along the conversion cycle. Since this need leads to complex and multiple capacitor-based DACs [2], this design uses a Kelvin divider and an effective switch-selection network. Moreover, dynamic bit registers and synchronous successive approximation operation avoid the possible speed bottleneck established by a conventional SAR logic. Figure 10.5.1 shows the block diagram of the proposed architecture. The shift registers control 170 switches to provide two differential reference voltages, V rH and V rL . Two sampling front-ends generate the difference between input and references. The differential signals serve a 3-level interpolation network with three fast comparators. An on-chip foreground offset calibration circuit minimizes the offset of the comparators. The scheme adjusts the comparator offset with digitally controlled MOS-capacitance located at the output of the comparator. The use of interpolation reduces the number of switches and shift registers, and results in diminishing consumed power and area. Figure 10.5.2 shows the schematic of the sampling front end. Capacitors C S sample the input signal during the sampling phase, Φ S , and hold it for the entire conversion period. The reference voltages at the left terminal of C S shift the differential voltages V in at the comparator input. The use of a resistive DAC enables a very fast settling with a relatively small dynamic and reasonable power, since it is required to charge only the parasitic capacitances including the parasitics of switches, input capacitance of the comparator and parasitics of the C S , but not the C S itself due to the high-impedance node at the comparator input.Clock feed-through occurring when sampling the input signal is a key limit to the overall accuracy. Bootstrapping the sampling switch, driven with an almost constant V GS , minimizes the clock feed-through. However, the rising edge of the bootstrapped clock phase depends on V in . This determines a second-order signal-dependent clock feed-through term that is alleviated by the cross-connected capacitance C C . The value of C C matches the parasitic C gd of M SW . Figure 10.5.3 shows the ...

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