A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS

Chan, Chi-Hang; Zhu, Yan; Chio, U-Fat; Sin, Sai-Weng; Seng-Pan, U; Martins, Rui P.

doi:10.1109/asscc.2011.6123645

Cited by 51 publications

(49 citation statements)

References 5 publications

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“…In Fig.7(a), the fitting equation between V ni (1σ value) and N is V ni = 212/ √ 2N µV , indicating the maximum noise (N=1) for this comparator is about 150 µV. Compared with conventional comparators whose noises always exceed hundreds of µV [11] [12], this comparator has a lower noise level for all seven modes.…”

Section: B Noisementioning

confidence: 93%

A reconfigurable time-domain comparator for multi-sensing applications

Zhong

Wang

Bermak

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Wireless sensor network applications typically include various sensors (temperature, humidity, gas, etc.) and each sensor has different requirements of speed, noise, offset, and power consumption. In order to optimize the performance and allow long-time operation, reconfigurability is mostly desirable in the readout circuitry. In this paper, a reconfigurable time-domain comparator (RTDC) with low noise and low offset is proposed, mainly for reconfigurable SAR ADCs in wireless sensor nodes. With a supply voltage of 1.8 V, it can be dynamically reconfigured to operate in seven different modes for different sensing scenarios. From Mode 1 to Mode 7, the maximum operating speed of the comparator ranges from 182 MHz to 20 MHz with its input referred noise been reduced exponentially from 142 µV to 63.4 µV and its offset been reduced exponentially from 7.64 mV to 2.55 mV, respectively. The simulated energy efficiency is 1.27 pJ/conv in Mode 1 and it linearly increases to 9.48 pJ/conv in Mode 7. This wide operating range enables the best possible trade-off for the sensing node application at hand.

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Section: B Noisementioning

confidence: 93%

A reconfigurable time-domain comparator for multi-sensing applications

Zhong

Wang

Bermak

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…However, these preamplifiers should be designed with high bandwidth and gain, which significantly increases the power consumption. As a low-power alternative, there are several offset calibration techniques to suppress comparator offset errors [14,35,36]. In flash ADCs with high resolution, the offset requirement not only becomes more stringent, the number of comparators to be calibrated also increases exponentially; this makes such calibration systems more complicated while requiring more layout area for on-chip implementation.…”

Section: Interpolating and Folding Adcsmentioning

confidence: 99%

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Zahrai

Onabajo

2018

JLPEA

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This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6-8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.

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“…Most offset reduction methods involve similar principles: Offsets are caused by mismatches that lead to an imbalance between the two main branches of the differential comparator. Hence, to suppress the offset, an opposing imbalance can be introduced such as by adding capacitance ([2]- [3]) or by injecting current [4]. With addition of capacitance, the imbalance is generated through the differences in the charging and discharging rates at internal nodes.…”

Section: Introductionmentioning

confidence: 99%

Digitally programmable offset compensation of comparators in flash ADCs for hybrid ADC architectures

Zlochisti

Zahrai

Onabajo

2015

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

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This paper presents an offset calibration approach that exploits the dynamic characteristics of a comparator to achieve a wide linear tuning range by placing varactors at two different internal nodes: the drains of the input pairs ( nodes) for high linearity, and the output nodes for wider compensation range. The comparators are placed in a 3-bit 1GS/s flash ADC that will be integrated into an 8-bit hybrid ADC architecture. A digital calibration scheme controls the gate voltages of the varactors and detects the minimum offset condition. The proposed configuration was simulated with a transistor-level flash ADC design in 0.13µm CMOS technology and a Verilog-A behavioral implementation of the calibration circuitry. The ADC consumes 1.48mW of power (excluding the calibration circuitry, flip-flops and encoder) from a 1.2V voltage supply. Monte Carlo simulation results indicate that the method reduces the 3-sigma input offset of the comparator from 36.9mV to 1.6mV. The simulated effective number of bits (ENOB) of the flash ADC is 2.96 bits.

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A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS

Cited by 51 publications

References 5 publications

A reconfigurable time-domain comparator for multi-sensing applications

A reconfigurable time-domain comparator for multi-sensing applications

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Digitally programmable offset compensation of comparators in flash ADCs for hybrid ADC architectures

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