Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications
Tejender Singh,
Suman Lata Tripathi,
Mufti Mahmud
Abstract:This study gives a thorough analysis of the performance of a 45 nm CMOS process-designed 16-bit 500 MS/s successive approximation register analog-to-digital converter (SAR-ADC). 16-bit R-2R DAC double-tail dynamic latch, Widlar current method, variable body-biasing technique, sample and hold block, 16-bit SAR, and 16-bit latch are used to design proposed SAR-ADC block. The SAR-ADC design and simulations were carried out using Cadence Virtuoso software. This powerful electronic design automation (EDA) tool faci… Show more
Set email alert for when this publication receives citations?
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.