An Improved Design of Absolute-value Detector by Using Optimized Ripple Adder

Abstract

Absolute-value detector (AVD) is one of the most basic bit-operating devices, which compares the magnitude of two inputs. However, the traditional 4-bit AVD is not only time-consuming but also has a high energy consumption. This paper uses a hybrid design to optimize the 4-bit AVD by introducing an improved ripple adder in the absolute value extraction part, which then can be less energy-consuming and requires fewer transistors. The paper divides the design of AVD into an absolute value extraction part and a comparator. The input (2’s complement) can be positive or negative numbers in the absolute value extraction part. By observing the most significant bit (MSB) of the input, the design can determine the sign of input and output magnitude. For the comparator, this paper uses a logic of step-by-step comparison from the most to the least significant bits. Then, this paper finds the minimum delay of the design by critical path analysis and gate sizing. The final delay is set at 1.5 times its minimum. Device voltage optimization is applied for calculating the energy consumption. Finally, with 1.5 times the minimum delay, the energy consumption is 40% less than the consumption when the delay is the minimum.