Current multi-core design methodologies are facing increasing unpredictability in terms of quality due to the actual diversity of the workloads that characterize the deployment scenario. To this end, these systems expose a set of dynamic parameters which can be tuned at run-time to achieve a specified Quality of Service (QoS) in terms of performance. A run-time manager operating system module is in charge of matching the specified QoS with the available platform resources by manipulating the overall degree of task-level parallelism of each application as well as the frequency of operation of each of the system cores.In this paper, we introduce a design space exploration framework for enabling and supporting enhanced resource management through software re-configuration on an industrial multicore platform. From one side, the framework operates at design time to identify a set of promising operating points which represent the optimal trade-off in terms of the target power consumption and performance. The operating points are used after the system has been deployed to support an enhanced resource management policy. This is done by a light-weight resource management layer which filters and selects the optimal parallelism of each application and operating frequency of each core to achieve the QoS constraints imposed by the external world and/or the user.We show how the proposed design-time and run-time techniques can be used to optimally manage the resources of a multiple-stream MPEG4 encoding chip dedicated to automotive cognitive safety tasks 1 .

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Abstract-This paper presents a design space exploration of a selective load value prediction scheme suitable for energyaware Simultaneous Multi-Threaded (SMT) architectures. A load value predictor is an architectural enhancement which speculates over the results of a micro-processor load instruction to speedup the execution of the following instructions. The proposed architectural enhancement differs from a classic predictor due to an improved selection scheme that allows to activate the predictor only when a miss occurs in the first level of cache. We analyze the effectiveness of the selective predictor in terms of overall energy reduction and performance improvement. To this end, we show how the proposed predictor can produce benefits (in terms of overall cost) when the cache size of the SMT architecture is reduced and we compare it with a classic non-selective load value prediction scheme. The experimental results have been gathered with a state-of-the-art SMT simulator running the SPEC2000 benchmark suite, both in SMT and non-SMT mode.

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Abstract-In the context of a design space exploration framework for supporting the platform-based design approach, we address the problem of robustness with respect to manufacturing process variations. First, we introduce response surface modeling techniques to enable an efficient evaluation of the statistical measures of execution time and energy consumption for each system configuration. We then introduce a robust design space exploration framework to afford the problem of the impact of manufacturing process variations onto the system-level metrics and consequently onto the application-level constraints. We finally provide a comparison of our design space exploration technique with conventional approaches. 1 I. INTRODUCTION Process variation is dramatically becoming one of the most important challenges related to power and performance optimization for sub-90 nm CMOS technologies. Parametric yield, i.e., the percentage of dies that meet power and performance constraints, has become as important as power and performance optimization itself.Manufacturing process variability is mainly due to inter-die and intra-die variations. Inter and intra-die variations affect low level process parameters such as the channel gate length, the thickness of the oxide and the threshold voltage, which, in turn, affect the critical path delay and static and dynamic power consumption. Inter-die fluctuations affect uniformly every element on a die and consist of lot-to-lot and wafer-towafer variations such as processing temperatures, equipment properties, wafer polishing, wafer placement and the resist thickness. Conversely, intra-die parameter fluctuations consist of both random and systematic components and generate nonuniform electrical characteristics across the chip [1].In this scenario, we address the problem of variabilityaware design at system-level for chip multi-processors (CMP). More precisely, we tackle the problem of the impact of manufacturing process variations onto the system-level metrics and consequently onto the application-level constraints.The main contribution of this paper is twofold:• We introduce a design space exploration (DSE) framework which is robust with respect to manufacturing process variations. The main goal is the optimization of the dispersion of the target system metrics and the maximization of the yield of the system with respect to the application-level constraints.• The exploration process is supported by response surface modeling (RSM) techniques for improving the overall estimation time to obtain the system-level metrics associated to each system configuration. The DSE framework is based on a set of state-of-the-art accurate performance, area and energy models of a CMP

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