Variability-aware robust design space exploration of chip multiprocessor architectures

Abstract

Abstract-In the context of a design space exploration framework for supporting the platform-based design approach, we address the problem of robustness with respect to manufacturing process variations. First, we introduce response surface modeling techniques to enable an efficient evaluation of the statistical measures of execution time and energy consumption for each system configuration. We then introduce a robust design space exploration framework to afford the problem of the impact of manufacturing process variations onto the system-level metrics and consequently onto the application-level constraints. We finally provide a comparison of our design space exploration technique with conventional approaches. 1 I. INTRODUCTION Process variation is dramatically becoming one of the most important challenges related to power and performance optimization for sub-90 nm CMOS technologies. Parametric yield, i.e., the percentage of dies that meet power and performance constraints, has become as important as power and performance optimization itself.Manufacturing process variability is mainly due to inter-die and intra-die variations. Inter and intra-die variations affect low level process parameters such as the channel gate length, the thickness of the oxide and the threshold voltage, which, in turn, affect the critical path delay and static and dynamic power consumption. Inter-die fluctuations affect uniformly every element on a die and consist of lot-to-lot and wafer-towafer variations such as processing temperatures, equipment properties, wafer polishing, wafer placement and the resist thickness. Conversely, intra-die parameter fluctuations consist of both random and systematic components and generate nonuniform electrical characteristics across the chip [1].In this scenario, we address the problem of variabilityaware design at system-level for chip multi-processors (CMP). More precisely, we tackle the problem of the impact of manufacturing process variations onto the system-level metrics and consequently onto the application-level constraints.The main contribution of this paper is twofold:• We introduce a design space exploration (DSE) framework which is robust with respect to manufacturing process variations. The main goal is the optimization of the dispersion of the target system metrics and the maximization of the yield of the system with respect to the application-level constraints.• The exploration process is supported by response surface modeling (RSM) techniques for improving the overall estimation time to obtain the system-level metrics associated to each system configuration. The DSE framework is based on a set of state-of-the-art accurate performance, area and energy models of a CMP

Multifaceted Automated Analyses for Variability-Intensive Embedded Systems

“…Some system design frameworks [4], [41]- [48], model, assess and optimize quality attributes (NFB and NFOB), but do not capture nor manage all variability dimensions. Specific techniques attempt to efficiently handle either platform variability [49]- [51], application variability [52]- [55] or deployment variability [56], but they are limited to one dimension at a time and cannot reason on the whole problem.…”

Functional feasibility analysis of variability-intensive data flow-oriented applications over highly-configurable platforms

“…Some others try to handle some limited variability in platforms (e.g. optional resource, resource dependency, memories sizes) with reconfigurable architectures [21,20] [18]. To the best of our knowledge, none of these approaches handle variability in both application and platform sides so to assess the feasibility of our class of problem.…”

“…Current approaches [22,15,16] assess functional feasibility of constrained data-flow-oriented embedded systems, but do not capture nor manage variability at both levels. Some Ad hoc techniques are trying to handle either platform variability (as reconfigurable architectures [21,20] [18]) or functional variability (as multiple scenarios [19,25] or multi-modes systems [26,17]). On the other hand, approaches tackling both kinds of variability [12] are focusing on optimal platform selections to implement multiple functional variants at a lower cost, but they do not manage structural and behavioral properties (e.g.…”

Assessing the functional feasibility of variability-intensive data flow-oriented systems

“…Current approaches [15,16,23] assess functional feasibility of constrained data-flow-oriented embedded systems, but do not capture nor manage variability at both levels. Some Ad hoc techniques are trying to handle either platform variability (as reconfigurable architectures [21,22] [19]) or functional variability (as multiple scenarios [20,25] or multi-modes systems [18,26]). On the other hand, approaches tackling both kinds of variability [12] are focusing on optimal platform selections to implement multiple functional variants at a lower cost, but they do not manage structural and behavioral properties (e.g.…”