Instruction-level power estimation for embedded VLIW cores

Sami,; Sciuto,; Silvano,; Zaccaria,

doi:10.1109/hsc.2000.843703

Cited by 19 publications

(8 citation statements)

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“…The previous works on energy estimation of VLIW processors have several deficiencies. In [6], the power of an execution set of (ADD MAC) is approximated as power of (ADD NOP) added to (NOP MAC). This adds up the NOP energy twice in an execution set.…”

Section: Results and Conclusionmentioning

confidence: 99%

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An Accurate Energy Estimation Framework for VLIW Processor Cores

Roy¹,

Bhatia²,

Mathur³

2006

2006 International Conference on Computer Design

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Abstract-In this paper, we present a comprehensive energy estimation framework for software executing on Very Long Instruction Word (VLIW) processor cores. The proposed energy model is used as an average energy estimator coupled to the instruction set simulator (ISS) of the processor. The base energy of an execution set is computed as the NOP energy added with incremental energies of each instruction in the execution set. The inter execution-set energy is accurately modeled with a new approach as a linear equation of three factors -functional to functional instruction switching; functional to NOP or prefix instruction swithing; and variability in the length of the execution set. This reduces the characterization complexity of the model to O(N ), where N is the total number of instructions in the instruction set of the processor. We have introduced the concept of "functional separability" in the energy model, wherein the energy of each high-level function of the processor core is distinctly mapped to only one component in the model. The model is also capable of handling control codes with branches and predicated execution. The average error magnitude of the framework when applied on the StarCore processor with a large suite of DSP and control benchmarks is 2.5%, whereas the maximum error is less than 6.0%.

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Section: Results and Conclusionmentioning

confidence: 99%

“…Sami et.al. [6], [7] have proposed a basic model for VLIW processors. However this model has several limitations when applied on practical VLIW processors, as we discuss later.…”

Section: Introductionmentioning

confidence: 99%

An Accurate Energy Estimation Framework for VLIW Processor Cores

Roy¹,

Bhatia²,

Mathur³

2006

2006 International Conference on Computer Design

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“…At the instruction level, compile-time estimation of power consumption is possible using any of a wide variety of approaches [17,4,15]. Many of the techniques discussed in the literature use detailed architectural models, but such models are difficult to create and maintain for the processors and other subsystems commonly used in cluster nodes.…”

Section: Compiler Techniquesmentioning

confidence: 99%

Compiler and runtime support for predictive control of power and cooling

Dietz¹,

Dieter²

2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

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“…In [9,10], the same average energy is assumed for all instructions and the average power consumption while running an application program is calculated using the operating voltage of the processor and the clock frequency. In [11], the authors measure the average energy consumed in each pipeline stage of a VLIW processor using a cycle-accurate simulator (e.g., Trimaran [12]) to improve the accuracy. The techniques estimate the average energy consumption over the entire program execution, while many software-level energy optimization techniques need cycle-accurate energy estimation.…”

Section: Related Workmentioning

confidence: 99%

Processor Energy Characterization for Compiler‐Assisted Software Energy Reduction

Gauthier

Ishihara

2012

Journal of Electrical and Computer Engineering

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Energy consumption is a fundamental barrier in taking full advantage of today and future semiconductor manufacturing technologies. The paper presents our recent research activities and results on characterizing and reducing the energy consumption in embedded systems. Firstly, a technique for characterizing the energy consumption of embedded processors during an application execution is presented. The technique trains a per-processor linear approximation model for fitting it to the energy consumption of the processor obtained by postlayout simulation. Secondly, based on the energy model mentioned above, the paper shows techniques for reducing the energy consumption by optimally mapping program code, stack frames, and data items to the scratch-pad memory (SPM) of the processor memory space.

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Instruction-level power estimation for embedded VLIW cores

Cited by 19 publications

References 0 publications

An Accurate Energy Estimation Framework for VLIW Processor Cores

An Accurate Energy Estimation Framework for VLIW Processor Cores

Compiler and runtime support for predictive control of power and cooling

Processor Energy Characterization for Compiler‐Assisted Software Energy Reduction

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