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Four groups of grain sizes of LiF:Mg,Cu,P material were chosen for the experiment. The influences of the grain size on the photon energy response and dose response have been examined in the intewal of 28-1250 keV and the dose range 0.190 Gy of ' %o y-rays. The experimental results show that both the energy response and the dose response are grain size dependent. A possible correlation seems to exist between the energy response v(E) and the dose response f ( D ) . A brief discussion is provided.

By introducing high-purity and low-temperature Ar annealing at 850 °C, atomically flat Si surfaces of silicon-on-insulator (SOI) and shallow-trench-isolation (STI)-patterned wafers were obtained. In the case of the STI-patterned wafer, this low-temperature annealing and subsequent radical oxidation to form a gate oxide film were introduced into the complementary metal oxide semiconductor (CMOS) process with 0.22 µm technology. As a result, a test array circuit for evaluating the electrical characteristics of a very large number (>260,000) of metal oxide semiconductor field effect transistors (MOSFETs) having an atomically flat gate insulator/Si interface was successfully fabricated on a 200-mm-diameter wafer. By evaluating 262,144 nMOSFETs, it was found that not only the gate oxide reliability was improved, but also the noise amplitude of the gate–source voltage related to the random telegraph noise (RTN) was reduced owing to the introduction of the atomically flat gate insulator/Si interface.

Atomically flattening technology was introduced to the widely used complementary metal oxide silicon process employing sallow trench isolation at the 0.22-μm technology node. Two methods were investigated. The first method is to apply the atomically flattening to the starting Si wafer, and the second method is to apply this just before forming the gate oxide. In both methods, atomically flat gate insulator/Si interface could be obtained, and the test array circuit for evaluating the electrical characteristics of many (>130,000) metal oxide semiconductor field effect transistors was successfully fabricated on an entire 200-mm-diameter wafer. By evaluating the test circuit, the noise amplitude of the gate–source voltage related to the random telegraph noise was reduced owing to introducing the atomically flat gate insulator/Si interface. The charge-to-breakdown of the gate oxide was also improved.