Atomically flattening of Si surface of silicon on insulator and isolation-patterned wafers

Goto, Tetsuya; Kuroda, Rihito; Akagawa, Naoya; Suwa, Tomoyuki; Teramoto, Akinobu; Li, Xiang; Tatsunori, Obara; Kimoto, Daiki; Sugawa, Shigetoshi; Ohmi, Tadahiro; Kamata, Yutaka; Kumagai, Yoshinao; Shibusawa, K.

doi:10.7567/jjap.54.04da04

Cited by 12 publications

(16 citation statements)

References 27 publications

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“…5(b) for the atomically flat device had no adverse impact on the charge to breakdown of MOS devices. The result is consistent with the results of improvement of E BD for the atomically flat device having STI edge previously reported (10), or the results of breakdown characteristics of the MOS capacitors having the field-oxide-etched isolation patterns (6,7), demonstrating that the …”

Section: Small Active Area and Its Edgesupporting

confidence: 92%

Low Temperature Atomically Flattening of Si Surface of Shallow Trench Isolation Pattern

Goto¹,

Kuroda²,

Suwa³

et al. 2015

ECS Trans.

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Low temperature (800 ºC - 900 ºC) Ar annealing for atomically flattening was applied to shallow trench isolation (STI)-patterned wafers where Si and SiO2 coexist on the wafer surface. During the Ar annealing, concentrations of H2O and O2 residual gases in the annealing ambience was maintained at low level less than 30 ppb. Such low temperature and clean Ar ambience can suppress oxidation and etching of Si surface as well as a decomposition of thick SiO2 film for device isolation. As a result, the atomically flat Si surface was obtained for the Si active pattern having STI edge by the Ar annealing at 800 ºC - 900 ºC. Owing to the introduction of the atomically flat Si/gate oxide interface, breakdown characteristic of the fabricated MOS capacitors was improved for the atomically flat devices.

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Section: Small Active Area and Its Edgesupporting

confidence: 92%

Low Temperature Atomically Flattening of Si Surface of Shallow Trench Isolation Pattern

Goto¹,

Kuroda²,

Suwa³

et al. 2015

ECS Trans.

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“…Other studies have reported that the Si surface morphology appears to change at annealing temperatures of around 900 °C. [23][24][25] A possible explanation is that the oxygen atoms in the oxide layer at the SiN/Si or SiN/poly-Si interface can start to move at around 900 °C, which allows the atomic bonding structure to drastically change according to the Si reconstruction process. 26 This may cause the dangling bond densities at the SiN/Si interface to increase and to be detected as Pb centers and/or the M signal exhibiting a local maximum peak at around 900 °C.…”

Section: Resultsmentioning

confidence: 99%

Two Specific Behaviors of Breakdown Occurrence Depending on N₂ Annealing Temperature in Poly-Si/SiN/Poly-Si Capacitors

Kurita¹,

Nakamura²,

Miyagawa

et al. 2023

ECS J. Solid State Sci. Technol.

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A time-dependent dielectric breakdown assessment was performed on a poly-Si/SiN/poly-Si capacitor to investigate the dependence of the breakdown occurrence on the N2 annealing temperature. We identified two specific behaviors of the breakdown occurrence dependent on the N2 annealing temperature: a peak at around 900°C and a monotonic increase at temperatures above 1000°C. Electron spin resonance spectroscopy was used to observe defects in the SiN film on the Si substrate, and the two behaviors showed good correlations with two types of changes in the defect densities: Pb centers on the Si substrate at the SiN/Si interface and an unidentified spectrum showing a local maximum at 900°C; and E′ centers in the SiO2 film at the SiN/Si interface and K centers in the SiN film showing a monotonic increase at higher temperatures. We propose that the two specific behaviors of breakdown occurrence can be attributed to not only bulk defects in the SiN film but also defects near the SiN/Si interface.

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“…The interface roughness degrades not only electron mobility [66][67][68][69][70][71] and gate dielectric reliability [72][73][74], but also noise generation [71,75,76]. An atomically flat interface [77][78][79][80][81][82][83][84] is effective for reducing low-frequency noise [79,[83][84][85][86][87].…”

Section: Mosfets With Atomically Flat Gate Insulator/si Interfacementioning

confidence: 99%

Evaluation of Low-Frequency Noise in MOSFETs Used as a Key Component in Semiconductor Memory Devices

Teramoto

2021

Electronics

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Methods for evaluating low-frequency noise, such as 1/f noise and random telegraph noise, and evaluation results are described. Variability and fluctuation are critical in miniaturized semiconductor devices because signal voltage must be reduced in such devices. Especially, the signal voltage in multi-bit memories must be small. One of the most serious issues in metal-oxide-semiconductor field-effect-transistors (MOSFETs) is low-frequency noise, which occurs when the signal current flows at the interface of different materials, such as SiO2/Si. Variability of low-frequency noise increases with MOSFET shrinkage. To assess the effect of this noise on MOSFETs, we must first understand their characteristics statistically, and then, sufficient samples must be accurately evaluated in a short period. This study compares statistical evaluation methods of low-frequency noise to the trend of conventional evaluation methods, and this study’s findings are presented.

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Atomically flattening of Si surface of silicon on insulator and isolation-patterned wafers

Cited by 12 publications

References 27 publications

Low Temperature Atomically Flattening of Si Surface of Shallow Trench Isolation Pattern

Low Temperature Atomically Flattening of Si Surface of Shallow Trench Isolation Pattern

Two Specific Behaviors of Breakdown Occurrence Depending on N₂ Annealing Temperature in Poly-Si/SiN/Poly-Si Capacitors

Evaluation of Low-Frequency Noise in MOSFETs Used as a Key Component in Semiconductor Memory Devices

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Atomically flattening of Si surface of silicon on insulator and isolation-patterned wafers

Cited by 12 publications

References 27 publications

Low Temperature Atomically Flattening of Si Surface of Shallow Trench Isolation Pattern

Low Temperature Atomically Flattening of Si Surface of Shallow Trench Isolation Pattern

Two Specific Behaviors of Breakdown Occurrence Depending on N2 Annealing Temperature in Poly-Si/SiN/Poly-Si Capacitors

Evaluation of Low-Frequency Noise in MOSFETs Used as a Key Component in Semiconductor Memory Devices

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Two Specific Behaviors of Breakdown Occurrence Depending on N₂ Annealing Temperature in Poly-Si/SiN/Poly-Si Capacitors