Introduction of Atomically Flattening of Si Surface to Large-Scale Integration Process Employing Shallow Trench Isolation

Abstract

Atomically flattening technology was introduced to the widely used complementary metal oxide silicon process employing sallow trench isolation at the 0.22-μm technology node. Two methods were investigated. The first method is to apply the atomically flattening to the starting Si wafer, and the second method is to apply this just before forming the gate oxide. In both methods, atomically flat gate insulator/Si interface could be obtained, and the test array circuit for evaluating the electrical characteristics of many (>130,000) metal oxide semiconductor field effect transistors was successfully fabricated on an entire 200-mm-diameter wafer. By evaluating the test circuit, the noise amplitude of the gate–source voltage related to the random telegraph noise was reduced owing to introducing the atomically flat gate insulator/Si interface. The charge-to-breakdown of the gate oxide was also improved.

Evaluation of Low-Frequency Noise in MOSFETs Used as a Key Component in Semiconductor Memory Devices

“…We have to continue the evaluation of such miniaturized and new structure devices. To assess the effect of this noise on Figure 32 shows the Gumbel plot of V RMS for the atomically flat and conventional SiO 2 /Si interface [84]. The noise of the atomically flat interface is less than that of the conventional interface.…”

“…The interface roughness degrades not only electron mobility [66][67][68][69][70][71] and gate dielectric reliability [72][73][74], but also noise generation [71,75,76]. An atomically flat interface [77][78][79][80][81][82][83][84] is effective for reducing low-frequency noise [79,[83][84][85][86][87].…”

“…Figure 31 shows images of an atomically flat surface and as-received Si(100) measured by atomic force microscopy (AFM). The atomically flat surface was formed in the active region with shallow trench isolation and was measured after the gate oxide formation and following oxide stripping [84]. The average roughness (Ra) of the conventional surface is 0.12 nm, which is the same as the initial surface of Si(100).…”

“…Figure 32 shows the Gumbel plot of VRMS for the atomically flat and conventional SiO2/Si interface [84]. The noise of the atomically flat interface is less than that of the conventional interface.…”

“…This means that introducing the atomically flat interface is extremely effective for reducing RTN as well as 1/f noise [86][87][88]. The atomically flat surface was formed before gate oxidation in this experiment [84]. Although using trapezoidal MOSFETs in real electronic devices is difficult, changing the shape of MOSFETs is very useful to obtain much information about RTN characteristics.…”