Atomically flat interface for noise reduction in SOI-MOSFETs

Gaubert, Philippe; Kircher, Alexandre; Park, Hyeonwoo; Kuroda, Rihito; Sugawa, Shigetoshi; Goto, Tetsuya; Suwa, Tomoyuki; Teramoto, Akinobu

doi:10.1109/icnf.2017.7985986

Cited by 1 publication

(4 citation statements)

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“…The size of MOSFETs has been downscaled to less than l0 nm and the structure has changed the planer to FinFET, recently. We have to continue the evaluation of To implement the surface flattening process, a low temperature of less than 900 • C and low oxidation species, such as O 2 and H 2 O, must be required [81,82,85]. There is another method for flattening the surface first and keeping it during the process steps preceding gate oxidation [85,87,88].…”

Section: Discussionmentioning

confidence: 99%

“…We have to continue the evaluation of To implement the surface flattening process, a low temperature of less than 900 • C and low oxidation species, such as O 2 and H 2 O, must be required [81,82,85]. There is another method for flattening the surface first and keeping it during the process steps preceding gate oxidation [85,87,88]. Other problems exist, such as STI edge shape and dopant segregation, and the solutions to these problems may affect not only MOSFET characteristics, but also noise [84].…”

Section: Discussionmentioning

confidence: 99%

“…The interface roughness degrades not only electron mobility [66][67][68][69][70][71] and gate dielectric reliability [72][73][74], but also noise generation [71,75,76]. An atomically flat interface [77][78][79][80][81][82][83][84] is effective for reducing low-frequency noise [79,[83][84][85][86][87].…”

Section: Mosfets With Atomically Flat Gate Insulator/si Interfacementioning

confidence: 99%

“…The average roughness in the trace of the atomically flat interface was less than 0.04 nm, which is the detection limit of our AFM system. L = 0.135 tan θ (nm) (16) To implement the surface flattening process, a low temperature of less than 900 °C and low oxidation species, such as O2 and H2O, must be required [81,82,85]. There is another method for flattening the surface first and keeping it during the process steps preceding gate oxidation [85,87,88].…”

Section: Mosfets With Atomically Flat Gate Insulator/si Interfacementioning

confidence: 99%

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Evaluation of Low-Frequency Noise in MOSFETs Used as a Key Component in Semiconductor Memory Devices

Teramoto

2021

Electronics

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Methods for evaluating low-frequency noise, such as 1/f noise and random telegraph noise, and evaluation results are described. Variability and fluctuation are critical in miniaturized semiconductor devices because signal voltage must be reduced in such devices. Especially, the signal voltage in multi-bit memories must be small. One of the most serious issues in metal-oxide-semiconductor field-effect-transistors (MOSFETs) is low-frequency noise, which occurs when the signal current flows at the interface of different materials, such as SiO2/Si. Variability of low-frequency noise increases with MOSFET shrinkage. To assess the effect of this noise on MOSFETs, we must first understand their characteristics statistically, and then, sufficient samples must be accurately evaluated in a short period. This study compares statistical evaluation methods of low-frequency noise to the trend of conventional evaluation methods, and this study’s findings are presented.

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