We investigated the reduction of current fluctuations in few-layer black phosphorus (BP) field-effect transistors resulting from Al2O3 passivation. In order to verify the effect of Al2O3 passivation on device characteristics, measurements and analyses were conducted on thermally annealed devices before and after the passivation. More specifically, static and low-frequency noise analyses were used in monitoring the charge transport characteristics in the devices. The carrier number fluctuation (CNF) model, which is related to the charge trapping/detrapping process near the interface between the channel and gate dielectric, was employed to describe the current fluctuation phenomena. Noise reduction due to the Al2O3 passivation was expressed in terms of the reduced interface trap density values D(it) and N(it), extracted from the subthreshold slope (SS) and the CNF model, respectively. The deviations between the interface trap density values extracted using the SS value and CNF model are elucidated in terms of the role of the Schottky barrier between the few-layer BP and metal contact. Furthermore, the preservation of the Al2O3-passivated few-layer BP flakes in ambient air for two months was confirmed by identical Raman spectra.

Top‐gate ferroelectric memory transistors with single‐ to triple‐layered MoS2 nanosheets adopting poly(vinylidenefluoride‐trifluoroethylene) [P(VDF‐TrFE)] are demonstrated. The nonvolatile memory transistor with a single‐layer MoS2 channel exhibits excellent retention properties for more than 1000 s, maintaining ~5 × 103 for the program/erase ratio and displaying a high mobility of ~220 cm2/(V·s).

Black phosphorus (BP) nanosheet is two-dimensional (2D) semiconductor with distinct band gap and attracting recent attention from researches because it has some similarity to gapless 2D semiconductor graphene in the following two aspects: single element (P) for its composition and quite high mobilities depending on its fabrication conditions. Apart from several electronic applications reported with BP nanosheet, here we report for the first time BP nanosheet-ZnO nanowire 2D-1D heterojunction applications for p-n diodes and BP-gated junction field effect transistors (JFETs) with n-ZnO channel on glass. For these nanodevices, we take advantages of the mechanical flexibility of p-type conducting of BP and van der Waals junction interface between BP and ZnO. As a result, our BP-ZnO nanodimension p-n diode displays a high ON/OFF ratio of ∼10(4) in static rectification and shows kilohertz dynamic rectification as well while ZnO nanowire channel JFET operations are nicely demonstrated by BP gate switching in both electrostatics and kilohertz dynamics.

sputter-deposition and photolithography. As a result, we found a unique property of graphene electrode, which not only showed superior ohmic or ON current behavior to those of Au/Ti but also more enhanced OFF state behavior as well. We regard that such positive results are attributed to gate-voltage-induced work function tuning in exfoliated graphene.A scanning electron microscopy (SEM) image in Figure 1 a shows 30-µm-long MoS 2 fl ake that we placed on 285-nm-thick SiO 2 /p + -Si substrate, where two Au/Ti electrodes are deposited on MoS 2 while two graphene fl akes are placed on the same MoS 2 . The graphene electrodes are then connected to Au/Ti lead lines, as shown in the overall device scheme of Figure 1 b. Figure 1 c illustrates an initial device process step where the MoS 2 exfoliation by polydimethylsiloxane (PDMS) stamp and its transfer to SiO 2 /p + -Si substrate are performed, while another similar steps for graphene transfer are also shown in Figure 1 d where in fact we use an optical microscope (OM) to fi nd the initially-transferred MoS 2 channel fl ake and to align the graphene S/D fl akes on the MoS 2 channel fl ake (note the four arrows indicating such fl ake alignment by substrate stage movement). Since the contact needs some pressure (to red arrow direction) between graphene and device substrate, we call this contact method "direct imprint" and more details were recently introduced elsewhere. [ 38 ] After the two graphene S/D electrodes were properly arranged, Au/Ti (50 nm/25 nm) contact electrodes were patterned by photolithography and DC sputter-deposition/liff-off processes as respectively shown in Figure 1 e,f, to contact both MoS 2 and graphene electrodes once and for all. Figure 1 f is a schematic version of SEM image in Figure 1 a. Since we initially assumed that our long MoS 2 should have a uniform thickness in every location, it was necessary to experimentally measure the thickness of at least two important locations in Figure 2 a (an OM version of Figure 1 a): a central location (MoS 2 I) between graphene electrodes and another central location (MoS 2 II) between Au/Ti electrodes.According to atomic force microscopy scan results, the thicknesses of those two regions appear almost the same, to be ≈5 nm (7≈8 L) (see Figure 2 b,c). We also measured the thicknesses of two graphene S/D fl akes, which appear 15 and 12 nm for Gr1 and Gr2, respectively (see Figure 2 d,e). Figure 3 a displays the drain current-gate voltage ( I D -V G ) transfer characteristics obtained from both MoS 2 nanosheet FETs with graphene and Au/Ti S/D contacts, which have not Field-Effect TransistorsMechanically-exfoliated or chemical vapor deposited graphene has been extensively studied for any practical usages as the most well-known two dimensional (2D) nanosheet, since it was found and developed. [1][2][3][4][5][6] One of the practical applications was a source/drain (S/D) electrode [7][8][9][10][11][12][13][14][15] for such a variety of transistors as organic thin-fi lm transistors, [ 11 ] Si-based transistors, [ ...

Two-dimensional van der Waals (2D vdWs) materials are a class of new materials that can provide important resources for future electronics and materials sciences due to their unique physical properties. Among 2D vdWs materials, black phosphorus (BP) has exhibited significant potential for use in electronic and optoelectronic applications because of its allotropic properties, high mobility, and direct and narrow band gap. Here, we demonstrate a few-layered BP-based nonvolatile memory transistor with a poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric top gate insulator. Experiments showed that our BP-based ferroelectric transistors operate satisfactorily at room temperature in ambient air and exhibit a clear memory window. Unlike conventional ambipolar BP transistors, our ferroelectric transistors showed only p-type characteristics due to the carbon-fluorine (C-F) dipole effect of the P(VDF-TrFE) layer, as well as the highest linear mobility value of 1159 cm(2) V(-1) s(-1) with a 10(3) on/off current ratio. For more advanced memory applications beyond unit memory devices, we implemented two memory inverter circuits, a resistive-load inverter circuit and a complementary inverter circuit, combined with an n-type molybdenum disulfide (MoS2) nanosheet. Our memory inverter circuits displayed a clear memory window of 15 V and memory output voltage efficiency of 95%.

Lead sulfide (PbS) quantum dots (QDs) have great potential in optoelectronic applications because of their desirable characteristics as a light absorber for near-infrared (NIR) photodetection. However, most PbS-based NIR photodetectors are two-terminal devices, which require an integrated pixel circuit to be practical photosensors. Here we report on PbS QD/indium gallium zinc oxide (InGaZnO, IGZO) metal oxide semiconductor hybrid phototransistors with a photodetection capability between 700 and 1400 nm, a range that neither conventional Si nor InGaAs photodetectors can cover. The new hybrid phototransistor exhibits excellent photoresponsivity of over 10 6 A W − 1 and a specific detectivity in the order of 10 13 Jones for NIR (1000 nm) light. Furthermore, we demonstrate an NIR (1300 nm) imager using photogating inverter pixels based on PbS/IGZO phototransistors at an imaging frequency of 1 Hz with a high output voltage photogain of~4.9 V (~99%). To the best of our knowledge, this report demonstrates the first QD/metal oxide hybrid phototransistor-based flat panel NIR imager. Our hybrid approach using QD/metal oxide paves the way for the development of gate-tunable and highly sensitive flat panel NIR sensors/ imagers that can be easily integrated.

Recently, α-MoTe , a 2D transition-metal dichalcogenide (TMD), has shown outstanding properties, aiming at future electronic devices. Such TMD structures without surface dangling bonds make the 2D α-MoTe a more favorable candidate than conventional 3D Si on the scale of a few nanometers. The bandgap of thin α-MoTe appears close to that of Si and is quite smaller than those of other typical TMD semiconductors. Even though there have been a few attempts to control the charge-carrier polarity of MoTe , functional devices such as p-n junction or complementary metal-oxide-semiconductor (CMOS) inverters have not been reported. Here, we demonstrate a 2D CMOS inverter and p-n junction diode in a single α-MoTe nanosheet by a straightforward selective doping technique. In a single α-MoTe flake, an initially p-doped channel is selectively converted to an n-doped region with high electron mobility of 18 cm V s by atomic-layer-deposition-induced H-doping. The ultrathin CMOS inverter exhibits a high DC voltage gain of 29, an AC gain of 18 at 1 kHz, and a low static power consumption of a few nanowatts. The results show a great potential of α-MoTe for future electronic devices based on 2D semiconducting materials.

We have fabricated dual gate field effect transistors (FETs) with 12 nm-thin black phosphorus (BP) channel on glass substrate, where our BP FETs have a patterned-gate architecture with 30 nm-thick Al2O3 dielectrics on top and bottom of a BP channel. Top gate dielectric has simultaneously been used as device encapsulation layer, controlling the threshold voltage of FETs as well when FETs mainly operate under bottom gate bias. Bottom, top, and dual gate-controlling mobilities were estimated to be 277, 92, and 213 cm(2)/V s, respectively. Maximum ON-current was measured to be ∼5 μA at a drain voltage of -0.1 V but to be as high as ∼50 μA at -1 V, while ON/OFF current ratio appeared to be 3.6 × 10(3) V. As a result, our dual gate BP FETs demonstrate organic light emitting diode (OLED) switching for green and blue OLEDs, also demonstrating NOR logic functions by separately using top- and bottom-input.