MoS<sub>2</sub> Nanosheets for Top‐Gate Nonvolatile Memory Transistor Channel

Lee, Hee Sung; Min, Sung Kil; Park, Min Kyu; Lee, Young Tack; Jeon, Pyo Jin; Kim, Jae-Hoon; Ryu, Sunmin; Im, Seongil

doi:10.1002/smll.201200752

Cited by 234 publications

(198 citation statements)

References 37 publications

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“…The presence of defects in photodetectors can be beneficial since it has been shown to immobilize charges at the channel which improves the gain in photodetectors [14] and produces nonvolatile memory mechanisms. [15] On the other hand, large hysteresis caused, for example, by charge traps [2] and significant Schottky barriers [16] at the metal-semiconductor interface are still a major design challenge for the realization of novel device architectures. They have been shown to cause degradation in the performance of transistors [17] and generate high levels of flicker noise.…”

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confidence: 99%

Role of Charge Traps in the Performance of Atomically Thin Transistors

et al. 2017

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The emerging family of atomically thin materials is fueling the development of conceptually new technologies [1] in highly efficient optoelectronics [2,3] and photonic applications, [4] to name a few. The large variety of bandgap values found in layered transition-metal dichalcogenides (TMDCs) [5,6] make these materials especially suited for transistor applications. TMDCs are compounds with the general formula MX 2 , where M is a transition metal, e.g., Mo and W, and X is an element of the chalcogen group, S, Se, and Te. They appear in a layered structure where the metal forms a hexagonal plane and the chalcogenides are positioned over and under this plane in either a trigonal prismatic (2H), as shown in Figure 1a, or octahedral (1T) stacking configuration. [7] In the semiconducting 2H systems, the compounds show a transition from indirect bandgap in bulk materials to direct bandgap in single layers. [8] Transient currents in atomically thin MoTe 2 field-effect transistors (FETs) are measured during cycles of pulses through the gate electrode. The curves of the transient currents are analyzed in light of a newly proposed model for charge-trapping dynamics that renders a time-dependent change in the threshold voltage as the dominant effect on the channel hysteretic behavior over emission currents from the charge traps. The proposed model is expected to be instrumental in understanding the fundamental physics that governs the performance of atomically thin FETs and is applicable to the entire class of atomically thin-based devices. Hence, the model is vital to the intelligent design of fast and highly efficient optoelectronic devices.Single-and few-layered TMDCs have been implemented in a wide range of applications, ranging from thin film transistors, [9] digital electronics and optoelectronics, [2,10,11] flexible electronics, [12] and up to energy conversion and storage devices. [13] However, the defect states in TMDCs have an ambivalent nature and can have a major positive or negative impact on the performance of atomically thin devices. The presence of defects in photodetectors can be beneficial since it has been shown to immobilize charges at the channel which improves the gain in photodetectors [14] and produces nonvolatile memory mechanisms. [15] On the other hand, large hysteresis caused, for example, by charge traps [2] and significant Schottky barriers [16] at the metal-semiconductor interface are still a major design challenge for the realization of novel device architectures. They have been shown to cause degradation in the performance of transistors [17] and generate high levels of flicker noise. [18,19] To overcome these challenges, hysteresis is usually avoided by encapsulation [20,21] or operation under high vacuum. [22,23] Most of the current research into surface states of TMDCs has focused on the chemical origins of charge trapping. A full understanding of their effect on the electrical properties is still lacking, hindering the optimization of functional components. While hysteresis has been sho...

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Role of Charge Traps in the Performance of Atomically Thin Transistors

et al. 2017

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“…For example, a robust trap related hysteresis (often called the 'anti-hysteresis') has been observed in multiple studies [6][7][8][9] . A real ferroelectric induced hysteresis is rare [10][11][12] . Similarly, ferroelectric control of the channel charge for 2D transition metal dichalcogenides (TMDs) has proved to be significantly challenging [13][14][15] .…”

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Nonvolatile MoS2 field effect transistors directly gated by single crystalline epitaxial ferroelectric

Serrao

Khan

et al. 2017

Applied Physics Letters

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Abstract:We demonstrate non-volatile, n-type, back-gated, MoS2 transistors, placed directly on an epitaxial grown, single crystalline, PbZr0.2Ti0.8O3 (PZT) ferroelectric. The transistors show decent ON current (19 μA/μm), high on-off ratio (10 7 ), and a subthreshold swing of (SS ~ 92 mV/dec) with a 100 nm thick PZT layer as the back gate oxide. Importantly, the ferroelectric polarization can directly control the channel charge, showing a clear anti-clockwise hysteresis. We have self-consistently confirmed the switching of the ferroelectric and corresponding change in channel current from a direct time-dependent measurement. Our results demonstrate that it is possible to obtain transistor operation directly on polar surfaces and therefore it should be possible to integrate 2D electronics with single crystalline functional oxides.

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“…In addition, the maximum gate leakage current of about 10 −12 A (see Figure S4 in the Supporting Information) is observed repeatedly in our memory devices, being much less than the ones (10 −10 A) of top‐gate FeFETs using P(VDF‐TrFE) as gate dielectrics,11, 16, 31 in which this smaller leakage can be attributed to the much smaller functional area of the side‐gated structure (i.e., only the tip of the gate electrode). Furthermore, Figure 2c gives the transfer characteristics of the device with different source–drain bias ranging from 10 mV to 1 V. It is clear that the curve does not significantly shift with the increase of source–drain bias for the same V gs sweep range, which suggests a good transistor characteristic for these side‐gated devices.…”

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Side‐Gated In₂O₃ Nanowire Ferroelectric FETs for High‐Performance Nonvolatile Memory Applications

Yang

Liao

et al. 2016

Advanced Science

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A new type of ferroelectric FET based on the single nanowire is demonstrated. The design of the side‐gated architecture not only simplifies the manufacturing process but also avoids any postdeposition damage to the organic ferroelectric film. The devices exhibit excellent performances for nonvolatile memory applications, and the memory hysteresis can be effectively modulated by adjusting the side‐gate geometries.

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MoS₂ Nanosheets for Top‐Gate Nonvolatile Memory Transistor Channel

Cited by 234 publications

References 37 publications

Role of Charge Traps in the Performance of Atomically Thin Transistors

Role of Charge Traps in the Performance of Atomically Thin Transistors

Nonvolatile MoS2 field effect transistors directly gated by single crystalline epitaxial ferroelectric

Side‐Gated In₂O₃ Nanowire Ferroelectric FETs for High‐Performance Nonvolatile Memory Applications

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MoS2 Nanosheets for Top‐Gate Nonvolatile Memory Transistor Channel

Cited by 234 publications

References 37 publications

Role of Charge Traps in the Performance of Atomically Thin Transistors

Role of Charge Traps in the Performance of Atomically Thin Transistors

Nonvolatile MoS2 field effect transistors directly gated by single crystalline epitaxial ferroelectric

Side‐Gated In2O3 Nanowire Ferroelectric FETs for High‐Performance Nonvolatile Memory Applications

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MoS₂ Nanosheets for Top‐Gate Nonvolatile Memory Transistor Channel

Side‐Gated In₂O₃ Nanowire Ferroelectric FETs for High‐Performance Nonvolatile Memory Applications