A hybrid-trench-isolation (HTI) technology is proposed to overcome the scaling limitations caused by the difficulty of gate thinning and increased soft error rate at the 0.1 pn era. It is revealed that a significant speed improvement against bulk is achieved by using the body-tied structure without floating-body-related speed deterioration. A two-order reduction in the soft error rate for an HTI-SO1 4M-bit SRAM was demonstrated as compared with bulk one. Moreover, it is presented that full trench isolation in the HTI offers excellent isolation characteristics to realize the one-chip integration of analog and digital LSI's. It is concluded that SO1 technology with the HTI structure is one of the solutions against the scaling limitations.
IntroductionAggressively scaled-down CMOS technology faces the scaling barriers of the silicon technology. Two of the crucial issues are speed-improvement degradation and soft-error-rate increase. The difficulty of gate-oxide thinning spoils performance improvements. The reduction of the supply voltage and device dimension increases soft error rate. The theme of this paper is whether Silicon-&-Insulator (SOI) can break through scaling barriers. It is reported that the SO1 is substantially efficient against these issues [l, 21. However, its effectiveness have not discussed in detail at around the 0.1 pm generation. Especially, the floating-body effects are suggested to be the critical problem to obtain the SOI's performance gain in the 0.1 pn generation [3, 41. To extract the inherent feature of the SOI, we have proposed the hybrid-trench-isolation (HTI) structure, featuring body-tied transistor's with ideal and stable characteristics [5-71. In this paper, we reveal the distinct validity of the HTI-SO1 technology beyond the silicon technology crisis by investigating the speed performance, soft error rate, and signal isolation characteristics.
Actively Body-bias Controlled (ABC) SO1 SRAM that has a new cell structure including connections of the access and the driver transistor's bodies to the word line is proposed to realize low-voltage operation. We developed the direct body contact technology to apply forward biases to the bodies without area penalties and increases of parasitic gate capacitances by using the hybrid trench isolation [l] for the first time. Moreover, the standby current does not change because the body bias is not applied when the word-line voltage is low level. It is successfully demonstrated that low-voltage and high-speed operation is achieved by using the ABC SO1 SRAM.
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