Impact of actively body-bias controlled (ABC) SOI SRAM by using direct body contact technology for low-voltage application

Hirano, Y.; Ippóshi, T.; Dang, Hung; Matsumoto, Takuma; Iwamatsu, T.; Nii, Koji; Tsukamoto, Yasumasa; Yoshizawa, T.; Kato, Hiromitsu; Maegawa, Satoru; Arimoto, Kazutami; Inoue, Yasuo; Inuishi, M.; Ohji, Yuzuru

doi:10.1109/iedm.2003.1269160

Cited by 16 publications

(11 citation statements)

References 1 publication

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“…Once the via design rules have been relaxed like above, we can define the concept of a "routing via" when the via layer is used for routing in conjunction with the metal layer above (and optionally below) the via layer. A similar concept is used in high-density SRAM design under the name of "shared contacts" [4] in order to suggest the sharing of the same long contact to poly and diffusion, and was also proposed as a general method under the name "slotted vias" [10] in order to suggest the shape of the trenches (or "slots") for such elongated vias. In this paper we prefer the name "routing vias" in order to suggest the use of the via structure for actual routing of signals, not only for contacting between two metal layers.…”

Section: Routing Viasmentioning

confidence: 98%

Electromigration-aware design

Stan

2009

2009 European Conference on Circuit Theory and Design

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The most common wearout phenomena that impact reliability are: metal electromigration (EM), time-dependent dielectric breakdown (TDDB), hot carrier induced damage (HCID), negative bias temperature instability (NBTI) and thermal cycling. This paper focuses on electromigration and proposes two novel solutions. The first is the use of routing (or slotted) vias for improving electromigration performance for dual damascene copper interconnect without increasing the lateral dimensions of the wires. The second is the use of electromigration "reliability sensors" in order to detect impending failure of interconnect. The proposed solutions show good results in simulations and measurements of test structures.

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Section: Routing Viasmentioning

confidence: 98%

Electromigration-aware design

Stan

2009

2009 European Conference on Circuit Theory and Design

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“…The Active Body-biasing Controlled (ABC)-SOI capacitor utilizing the PD-SOI process with the Hybrid Trench Isolation technology [11], [12] provides a strong capacitive coupling. The strength of capacitive coupling is dependent upon a transistor size and gate voltage.…”

Section: A Abc-soi Capacitormentioning

confidence: 99%

Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation

Iijima¹,

Seto²,

Numa³

et al. 2008

JCP

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Instability of SRAM memory cells derived from the process variation and lowered supply voltage has recently been posing significant design challenges for low power SoCs. This paper presents a boosted word line voltage scheme, where an active bodybiasing controlled boost transistor generates a pulsed word line voltage by capacitive coupling only when accessed. Simulation results have shown that the proposed approach not only shortens the access time but mitigates the impact of Vth variation on performance even at ultra low supply voltage less than 0.5 V.

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“…There have many techniques been proposed to speed up LSI performance and to lower power supply voltages ( [1]- [3].) But they are not enough stable against PVT (Process, Voltage and Temperature) variation.…”

Section: Introduction Soi Devices Have Several Advantages Comparedmentioning

confidence: 99%

An Automatic Source/Body Level Controllable 0.5V level SOI Circuit Technique for Mobile and Wireless Network Applications

Okamura

Morishita

Dosaka

et al. 2006

2006 International Symposium on Communications and Information Technologies

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SOI device has the better potential of high speed, low operating voltage and RF functions like as mobile and wireless network applications. Gate Body directly connected SOI MOSFET without historical effects is one of the promised technologies that let the logic circuitry work in ultra low voltage. Compared to Bulk-Si MOSFET, GBSOI can reduce its power supply voltage by 30%, its current by 26% and its power dissipation by 47%. However sub-Gbps level clocking circuits with ultra low voltage require the smaller PVT (process, voltage and temperature) variation. This paper presents an architecture to stabilize SOI logic circuitry against PVT variation especially under ultra low power supply voltage. Deviation of gate delay caused by PVT variation is reduced to 1.6%, while 40% with Bulk-Si.This system realizes the cell libraries whose gate delay is constant despite PVT variation. They greatly help designing circuitry especially under ultra low voltage.

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Impact of actively body-bias controlled (ABC) SOI SRAM by using direct body contact technology for low-voltage application

Cited by 16 publications

References 1 publication

Electromigration-aware design

Electromigration-aware design

Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation

An Automatic Source/Body Level Controllable 0.5V level SOI Circuit Technique for Mobile and Wireless Network Applications

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