Inheritance of the apoE4 allele (4) increases the risk of developing Alzheimer's disease; however, the mechanisms underlying this association remain elusive. Recent data suggest that inheritance of 4 may lead to reduced apoE protein levels in the CNS. We therefore examined apoE protein levels in the brains, CSF and plasma of 2/2, 3/3, and 4/4 targeted replacement mice. These apoE mice showed a genotype-dependent decrease in apoE levels; 2/2 Ͼ3/3 Ͼ4/4. Next, we sought to examine the relative contributions of apoE4 and apoE3 in the 3/4 mouse brains. ApoE4 represented 30 -40% of the total apoE. Moreover, the absolute amount of apoE3 per allele was similar between 3/3 and 3/4 mice, implying that the reduced levels of total apoE in 3/4 mice can be explained by the reduction in apoE4 levels. In culture medium from 3/4 human astrocytoma or 3/3, 4/4 and 3/4 primary astrocytes, apoE4 levels were consistently lower than apoE3. Secreted cholesterol levels were also lower from 4/4 astrocytes. Pulse-chase experiments showed an enhanced degradation and reduced half-life of newly synthesized apoE4 compared with apoE3. Together, these data suggest that astrocytes preferentially degrade apoE4, leading to reduced apoE4 secretion and ultimately to reduced brain apoE levels. Moreover, the genotype-dependent decrease in CNS apoE levels, mirror the relative risk of developing AD, and suggest that low levels of total apoE exhibited by 4 carriers may directly contribute to the disease progression, perhaps by reducing the capacity of apoE to promote synaptic repair and/or A␤ clearance.

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The presenilin containing ␥-secretase complex is responsible for the regulated intramembraneous proteolysis of the amyloid precursor protein (APP), the Notch receptor, and a multitude of other substrates. ␥-Secretase catalyzes the final step in the generation of A␤ 40 and A␤ 42 peptides from APP. Amyloid ␤-peptides (A␤ peptides) aggregate to form neurotoxic oligomers, senile plaques, and congophilic angiopathy, some of the cardinal pathologies associated with Alzheimer's disease. Although inhibition of this protease acting on APP may result in potentially therapeutic reductions of neurotoxic A␤ peptides, nonselective inhibition of the enzyme may cause severe adverse events as a result of impaired Notch receptor processing. Here, we report the preclinical pharmacological profile of GSI-953 (begacestat), a novel thiophene sulfonamide ␥-secretase inhibitor (GSI) that selectively inhibits cleavage of APP over Notch. This GSI inhibits A␤ production with low nanomolar potency in cellular and cell-free assays of ␥-secretase function, and displaces a tritiated analog of GSI-953 from enriched ␥-secretase enzyme complexes with similar potency. Cellular assays of Notch cleavage reveal that this compound is approximately 16-fold selective for the inhibition of APP cleavage. In the human APP-overexpressing Tg2576 transgenic mouse, treatment with this orally active compound results in a robust reduction in brain, plasma, and cerebral spinal fluid A␤ levels, and a reversal of contextual fear-conditioning deficits that are correlated with A␤ load. In healthy human volunteers, oral administration of a single dose of GSI-953 produces dosedependent changes in plasma A␤ levels, confirming pharmacodynamic activity of GSI-953 in humans.This research was supported by Wyeth Research. Article, publication date, and citation information can be found at http://jpet.aspetjournals.org.

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With the help of HW/SW codesign, system-on-chip (SoC) can effectively reduce cost, improve reliability, and produce versatile products. The growing complexity of SoC designs makes on-chip communication subsystem design as important as computation subsystem design. While a number of codesign methodologies have been proposed for on-chip computation subsystems, many works are needed for on-chip communication subsystems. This paper proposes application-specific networkson-chip (ASNoC) and its design methodology. ASNoC is used for two high-performance SoC applications. The methodology (1) can automatically generate optimized ASNoC for different applications, (2) can generate a corresponding distributed shared memory along with an ASNoC, (3) can use both recorded and statistical communication traces for cycle-accurate performance analysis, (4) is based on standardized network component library and floorplan to estimate power and area, (5) adapts an industrial-grade network modeling and simulation environment, OPNET, which makes the methodology ready to use, and (6) can be easily integrated into current HW/SW codesign flow. Using the methodology, ASNoC is generated for a H.264 HDTV decoder SoC and Smart Camera SoC. ASNoC and 2D mesh networks-on-chip are compared in performance, power, and area in detail. The comparison results show that ASNoC provide substantial improvements in power, performance, and cost compared to 2D mesh networks-on-chip. In the H.264 HDTV decoder SoC, ASNoC uses 39% less power, 59% less silicon area, 74% less metal area, 63% less switch capacity, and 69% less interconnection capacity to achieve 2X performance compared to 2D mesh networks-on-chip.

Federated scheduling is a promising approach to schedule parallel real-time tasks on multi-cores, where each heavy task exclusively executes on a number of dedicated processors, while light tasks are treated as sequential sporadic tasks and share the remaining processors. However, federated scheduling suffers resource waste since a heavy task with processing capacity requirement x + (where x is an integer and 0 < < 1) needs x+1 dedicated processors. In the extreme case, almost half of the processing capacity is wasted. In this paper we propose the semifederate scheduling approach, which only grants x dedicated processors to a heavy task with processing capacity requirement x+ , and schedules the remaining part together with light tasks on shared processors. Experiments with randomly generated task sets show the semi-federated scheduling approach significantly outperforms not only federated scheduling, but also all existing approaches for scheduling parallel real-time tasks on multi-cores.

The geographic routing protocol only requires the location information of local nodes for routing decisions, and is considered very efficient in multi-hop wireless sensor networks. However, in dynamic wireless sensor networks, it increases the routing overhead while obtaining the location information of destination nodes by using a location server algorithm. In addition, the routing void problem and location inaccuracy problem also occur in geographic routing. To solve these problems, a novel fuzzy logic-based geographic routing protocol (FLGR) is proposed. The selection criteria and parameters for the assessment of the next forwarding node are also proposed. In FLGR protocol, the next forward node can be selected based on the fuzzy location region of the destination node. Finally, the feasibility of the FLGR forwarding mode is verified and the performance of FLGR protocol is analyzed via simulation. Simulation results show that the proposed FLGR forwarding mode can effectively avoid the routing void problem. Compared with existing protocols, the FLGR protocol has lower routing overhead, and a higher packet delivery rate in a sparse network.

In this paper, we propose a novel approach to schedule conditional DAG parallel tasks, with which we can derive safe response time upper bounds significantly better than the state-of-the-art counterparts. The main idea is to eliminate the notorious timing anomaly in scheduling parallel tasks by enforcing certain order constraints among the vertices, and thus the response time bound can be accurately predicted off-line by somehow “simulating” the runtime scheduling. A key challenge to apply the timing-anomaly free scheduling approach to conditional DAG parallel tasks is that at runtime it may generate exponentially many instances from a conditional DAG structure. To deal with this problem, we develop effective abstractions, based on which a safe response time upper bound is computed in polynomial time. We also develop algorithms to explore the vertex orders to shorten the response time bound. The effectiveness of the proposed approach is evaluated by experiments with randomly generated DAG tasks with different parameter configurations.