Inspired by the great success of neural networks, graph convolutional neural networks (GCNs) are proposed to analyze graph data. GCNs mainly include two phases with distinct execution patterns. The Aggregation phase, behaves as graph processing, showing a dynamic and irregular execution pattern. The Combination phase, acts more like the neural networks, presenting a static and regular execution pattern. The hybrid execution patterns of GCNs require a design that alleviates irregularity and exploits regularity. Moreover, to achieve higher performance and energy efficiency, the design needs to leverage the high intra-vertex parallelism in Aggregation phase, the highly reusable inter-vertex data in Combination phase, and the opportunity to fuse phase-by-phase execution introduced by the new features of GCNs. However, existing architectures fail to address these demands.In this work, we first characterize the hybrid execution patterns of GCNs on Intel Xeon CPU. Guided by the characterization, we design a GCN accelerator, HyGCN, using a hybrid architecture to efficiently perform GCNs. Specifically, first, we build a new programming model to exploit the fine-grained parallelism for our hardware design. Second, we propose a hardware design with two efficient processing engines to alleviate the irregularity of Aggregation phase and leverage the regularity of Combination phase. Besides, these engines can exploit various parallelism and reuse highly reusable data efficiently. Third, we optimize the overall system via inter-engine pipeline for inter-phase fusion and priority-based off-chip memory access coordination to improve off-chip bandwidth utilization. Compared to the state-of-the-art software framework running on Intel Xeon CPU and NVIDIA V100 GPU, our work achieves on average 1509× speedup with 2500× energy reduction and average 6.5× speedup with 10× energy reduction, respectively. * Corresponding author is Xiaochun Ye and his email is yexi-aochun@ict.ac.cn.

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Multilevel converters have good potential in high power and high voltage applications due to their advantages of reduced voltage or current stress on power devices. In recent years, hybrid multilevel converter (HMC) have attracted increasing attention since less equipment is required. In this paper, the topologies and evolutions of HMCs are presented, where five topology derivation ways are given by using basic cells in series-parallel/parallel-series. Some general topologies or structures that are used to generate higher levels are also deducted. Then many existing HMCs can be derived, and new topologies of the HMC might be inspired. The capabilities of neutral point and FC voltage balancing control are investigated. The performance of the selected FC-based HMCs is analyzed. Finally, the verifications of operation principle and control strategies for the derived HMCs are carried out.